TRI-SQR-VCO_OTA
*SPICE Netlist generated by Advanced Sim server on 18.09.2025 11:37:43
.options MixedSimGenerated

*Schematic Netlist:
CC NetC_1 0 4.9645nF
CC_an NetC_an_1 NetC_an_2 1nF
XIC1A NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 Vee NetC_1 U_TRI ExtraNet_XIC1A_9
+ ExtraNet_XIC1A_10 Vcc U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
XIC1B NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 Vee NetC_1 U_TRI ExtraNet_XIC1B_9
+ ExtraNet_XIC1B_10 Vcc U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
XIC1C NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 Vee NetC_1 U_TRI ExtraNet_XIC1C_9
+ ExtraNet_XIC1C_10 Vcc U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
XIC1E NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 Vee NetC_1 U_TRI ExtraNet_XIC1E_9
+ ExtraNet_XIC1E_10 Vcc U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
XIC2A U_SQR_OTA U_SQR Vcc Vee U_SQR TL074
XIC2B 0 NetC_an_1 Vcc Vee NetIC2_7 TL074
XIC2C NetIC2_10 U_C Vcc Vee U_C TL074
XIC2D NetIC2_12 NetIC2_13 Vcc Vee U_SAW TL074
XIC3A 0 NetIC3_2 Vcc Vee U_in TL074
RR2 Vee U_TRI 20k
RR3 NetIC1_1 Vcc 56k
RR4a NetIC3_2 U_TRI 100k
RR4b U_in NetIC3_2 56k
RR_A 0 U_SQR_OTA 4.7k
RR_CV NetR_CV_1 NetIC2_10 59.941k
RR_E NetC_an_2 NetR_E_2 20k
RR_goofer NetR_goofer_1 NetIC3_2 1Meg
RR_lambda_T NetIC2_10 0 1.1k
RR_ref NetC_an_1 Vee 1.5Meg
RR_SAW_a NetIC2_13 U_in 10k
RR_SAW_b NetIC2_12 U_in 10k
RR_SAW_c U_SAW NetIC2_13 10k
RR_SAW_d 0 U_SAW 1k
RR_SAW_e U_SQR NetR_SAW_e_2 33k
RR_trim_a NetR_goofer_1 Vee 50k
RR_trim_b Vcc NetR_goofer_1 50k
RRoff NetIC3_2 Vee 650k
QT1 NetC_an_1 U_C NetC_an_2 2N2907
QT2 NetT2_3 0 NetC_an_2 2N2907
JT? 0 NetR_SAW_e_2 NetIC2_12 BF545B
VU_mess NetT2_3 NetIC1_16 0
VU_messref NetR_E_2 NetIC2_7 0
VU_neg 0 Vee 15
VU_pos Vcc 0 15
VU_var NetR_CV_1 0 1

.PLOT TRAN {v(U_SQR)} =PLOT(2) =AXIS(1) =NAME(U_SQR) =UNITS(V)
.PLOT TRAN {v(U_TRI)} =PLOT(1) =AXIS(1) =NAME(U_TRI) =UNITS(V)
.PLOT TRAN {v(U_SAW)} =PLOT(3) =AXIS(1) =NAME(U_SAW) =UNITS(V)
.PLOT TRAN {i(U_pos)*30} =PLOT(4) =AXIS(1) =NAME(P_Ges) =UNITS(W)

.OPTIONS ITL4=100 METHOD=GEAR MAXORD=2
*Selected Circuit Analyses:
.TRAN 1u 16m 10m 1u

*Models and Subcircuits:
* A dual opamp ngspice model
* file name: LM13700-DUAL.ckt
.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
+ 2out 2in- 2in+ 2Dbias 2ABin
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the 
*  material is illegal

*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
*                 7:00 A.M.--7:00 P.M.  U.S. Central Time
*                                (800) 272-9959
* For Applications support, contact the Internet address:
*  amps-apps@galaxy.nsc.com

* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\            
* LM13700 Dual Operational Transconductance Amplifier                 
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\                 
*
*                   Amplifier Bias Input
*                   | Diode Bias
*                   | | Positive Input
*                   | | | Negative Input
*                   | | | | Output
*                   | | | | | Negative power supply
*                   | | | | | | Buffer Input
*                   | | | | | | | Buffer Output
*                   | | | | | | | | Positive power supply
*                   | | | | | | | | |
.SUBCKT LM13700/NS  1 2 3 4 5 6 7 8 11
*
* Features:
* gm adjustable over 6 decades.
* Excellent gm linearity.
* Linearizing diodes.
* Wide supply range of +/-2V to +/-22V.
*
* Note:  This model is single-pole in nature and over-estimates
*       AC bandwidth and phase margin (stability) by over 2X.   
*       Although refinement may be possible in the future, please
*       use benchtesting to finalize AC circuit design.
* 
* Note: Model is for single device only and simulated
*       supply current is 1/2 of total device current.
*
******************************************************
* 
C1  6  4  4.8P
C2  3  6  4.8P
* Output capacitor  
C3  5  6  6.26P                                       
D1  2  4  DX
D2  2  3  DX
D3  11 21 DX
D4  21 22 DX
D5  1  26 DX
D6  26 27 DX
D7  5  29 DX
D8  28 5  DX
D10 31 25 DX
* Clamp for -CMR  
D11 28 25 DX                                        
* Ios source 
F1  4  3  POLY(1)   V6 1E-10 5.129E-2 -1.189E4 1.123E9 
F2  11 5  V2        1.022
F3  25 6  V3        1.0
F4  5  6  V1        1.022
* Output impedance 
F5  5  0  POLY(2)   V3 V7 0 0 0 0 1                  
G1  0  33 5         0 .55E-3
I1  11 6  300U
Q1  24 32 31        QX1
Q2  23 3  31        QX2
Q3  11 7  30        QZ
Q4  11 30 8         QY
V1  22 24 0V
V2  22 23 0V
V3  27 6  0V
V4  11 29 1.4
V5  28 6  1.2
V6  4  32 0V
V7  33 0  0V
.MODEL QX1 NPN (IS=5E-16     BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QY  NPN (IS=6E-15     BF=50)
.MODEL QZ  NPN (IS=5E-16     BF=266)  
.MODEL DX  D   (IS=5E-16)
.ENDS
*$
XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
.ends

*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
*             Non-Inverting Input
*             | Inverting Input
*             | | Positive Power Supply
*             | | | Negative Power Supply
*             | | | | Output
*             | | | | |
.SUBCKT TL074 1 2 3 4 5
C1   11 12 3.498E-12
C2    6  7 15E-12
DC    5 53 DX
DE   54  5 DX
DLP  90 91 DX
DLN  92 90 DX
DP    4  3 DX
BGND 99  0 V=V(3)*.5 + V(4)*.5
BB    7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+              I(VLP)*5E6 - I(VLN)*5E6
GA    6  0 11 12 282.8E-6
GCM   0  6 10 99 8.942E-9
ISS   3 10 DC 195E-6
HLIM 90  0 VLIM 1K
J1   11  2 10 JX
J2   12  1 10 JX
R2    6  9 100E3
RD1   4 11 3.536E3
RD2   4 12 3.536E3
RO1   8  5 150
RO2   7 99 150
RP    3  4 2.143E3
RSS  10 99 1.026E6
VB    9  0 DC 0
VC    3 53 DC 2.2
VE   54  4 DC 2.2
VLIM  7  8 DC 0
VLP  91  0 DC 25
VLN   0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074

*2N2907 MCE 5-27-97
*Ref: Motorola Small-Signal Device databook, Q4/94
*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)

*PHILIPS SEMICONDUCTORS        Version: 1.0
*Filename: BF545B.PRM        Date: Oct 1992
*
.MODEL  BF545B   NJF
+(
+             VTO = -2.3085E+000
+            BETA = 1.09045E-003
+          LAMBDA = 2.31754E-002
+              RD = 7.77648E+000
+              RS = 7.77648E+000
+              IS = 2.59121E-016
+            CGS  = 2.00000E-012
+            CGD  = 2.20000E-012
+              PB = 9.91494E-001
+              FC = 5.00000E-001
+)

.END