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https://github.com/erik-toth/audio-synth.git
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PCB main schematic progress
TOP done; MCU done; CV_GEN done; VCO done; PM done; VCA done; OS done; waiting for VCF; EXT waiting until VCF done
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@@ -1,5 +1,5 @@
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ETOTH-Amp_LM386
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*SPICE Netlist generated by Advanced Sim server on 08.12.2025 13:48:55
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*SPICE Netlist generated by Advanced Sim server on 17.12.2025 16:45:18
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.options MixedSimGenerated
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*Schematic Netlist:
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@@ -11,18 +11,19 @@ LL_Speaker 0 NetL_Speaker_2 0.1mH
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RR_POTA 0 NetR_POT_2 {10k * {POS}}
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RR_POTB NetR_POT_2 IN_FILT {10k - (10k * {POS})}
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RR_Speaker NetL_Speaker_2 OUT 4R
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RR_static1 NetIC1_3 NetR_POT_2 100k
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RR_static1 NetIC1_3 NetR_POT_2 75k
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RR_static2 0 NetIC1_3 10k
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VU_q VAP 0 10V
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VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
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.PLOT AC {MAG(v(OUT))} =PLOT(1) =AXIS(1) =NAME(A_Speaker)
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.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255)
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.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
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.OPTIONS METHOD=GEAR MAXORD=2
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*Selected Circuit Analyses:
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.AC DEC 50 22 22000
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.TRAN 90.91u 22.73m 0 90.91u
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.CONTROL
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SWEEP C_DCBLOCK_OUT LIST 100u 150u 220u 330u 470u 680u
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SWEEP POS LIST 1
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.ENDC
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*Global Parameters:
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