Merge branch 'main' of https://github.com/erik-toth/audio-synth

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/ETOTH-Amp_LM386.nsx

@@ -1,5 +1,5 @@
 ETOTH-Amp_LM386
-*SPICE Netlist generated by Advanced Sim server on 08.12.2025 13:48:55
+*SPICE Netlist generated by Advanced Sim server on 17.12.2025 16:45:18
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -11,18 +11,19 @@ LL_Speaker 0 NetL_Speaker_2 0.1mH
 RR_POTA 0 NetR_POT_2 {10k * {POS}}
 RR_POTB NetR_POT_2 IN_FILT {10k - (10k * {POS})}
 RR_Speaker NetL_Speaker_2 OUT 4R
-RR_static1 NetIC1_3 NetR_POT_2 100k
+RR_static1 NetIC1_3 NetR_POT_2 75k
 RR_static2 0 NetIC1_3 10k
 VU_q VAP 0 10V
 VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
 
-.PLOT AC {MAG(v(OUT))} =PLOT(1) =AXIS(1) =NAME(A_Speaker)
+.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255)
+.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
-.AC DEC 50 22 22000
+.TRAN 90.91u 22.73m 0 90.91u
 .CONTROL
-SWEEP C_DCBLOCK_OUT LIST 100u 150u 220u 330u 470u 680u
+SWEEP POS LIST 1
 .ENDC
 
 *Global Parameters:

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [ETOTH-Amp_LM386.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 13:33:33 On 08.12.2025
+Finished Output Generation At 16:43:39 On 17.12.2025

dev/analog/ETOTH-VOICE_MIXER/VOICE-MIXER/Project Outputs for VOICE-MIXER/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [VOICE-MIXER.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 14:35:22 On 10.09.2025
+Finished Output Generation At 17:19:12 On 13.12.2025

dev/analog/ETOTH-VOICE_MIXER/VOICE-MIXER/Project Outputs for VOICE-MIXER/VOICE-MIXER.nsx

@@ -1,16 +1,17 @@
 VOICE-MIXER
-*SPICE Netlist generated by Advanced Sim server on 10.09.2025 14:45:45
+*SPICE Netlist generated by Advanced Sim server on 14.12.2025 16:19:21
 .options MixedSimGenerated
 
 *Schematic Netlist:
-XIC1A 0 NetIC1_2 VCC VEE U_out TL074
+XIC1A VCM NetIC1_2 VAP 0 U_out TL074
-RR1 U_1 NetIC1_2 10k
+RR1 U_1 NetIC1_2 330k
-RR2 U_2 NetIC1_2 10k
+RR2 U_2 NetIC1_2 330k
-RR_K NetIC1_2 U_out 10k
+RR3 VAP NetIC1_2 620k
-VU_neg 0 VEE 12
+RR_K NetIC1_2 U_out 150k
-VU_pos VCC 0 12
+VU_neg VCM 0 5
-VU_sin1 U_1 0 DC 0 SIN(0 1 440 0 0 0) AC 1 0
+VU_pos VAP VCM 5
-VU_sin2 U_2 0 DC 0 SIN(0 1 880 0 0 0) AC 1 0
+VU_sin1 U_1 VCM DC 0 SIN(-1.3 2 440 0 0 0) AC 1 0
+VU_sin2 U_2 VCM DC 0 SIN(-1.3 2 440 0 0 0) AC 1 0
 
 .PLOT TRAN {v(U_out)} =PLOT(1) =AXIS(1) =NAME(U_out) =UNITS(V)
 .PLOT TRAN {v(U_1)} =PLOT(1) =AXIS(1) =NAME(U_1) =UNITS(V)

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [VCA_LM13700.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 13:14:07 On 06.12.2025
+Finished Output Generation At 13:07:34 On 14.12.2025

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx

@@ -1,5 +1,5 @@
 VCA_LM13700
-*SPICE Netlist generated by Advanced Sim server on 06.12.2025 16:21:09
+*SPICE Netlist generated by Advanced Sim server on 14.12.2025 13:07:43
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -12,17 +12,15 @@ XIC1C NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1C_9
 XIC1E NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1E_9
 + ExtraNet_XIC1E_10 VAP ExtraNet_XIC1E_12 ExtraNet_XIC1E_13 ExtraNet_XIC1E_14
 + ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
-RR1 NetIC1_14 IN 3k
+RR1 NetIC1_14 IN 3.3k
 RR2 OUT VCM 27k
 RR3 Uout 0 5.1k
-RR4 VCM NetIC1_14 1k
+RR4 VCM NetIC1_14 1.2k
-RR5 VCM NetIC1_13 1k
+RR5 VCM NetIC1_13 1.2k
 RR_B NetR_B_1 NetR_B_2 100k
 RR_BASE_GAIN NetIC1_16 NetR_BASE_GAIN_2 10k
-RR_D VAP NetIC1_15 5k
+RR_D VAP NetIC1_15 5.1k
-RR_GAINA NetR_BASE_GAIN_2 NetR_BASE_GAIN_2 {100k * {GAIN}}
+QT VAP NetR_B_1 NetR_BASE_GAIN_2 QBC547B
-RR_GAINB NetR_BASE_GAIN_2 NetR_GAIN_3 {100k - (100k * {GAIN})}
-QT VAP NetR_B_1 NetR_GAIN_3 QBC547B
 VU_VCO_EN NetR_B_2 0 DC 0 PULSE(3.3 0 0 4u 1u 20m 40m) AC 1 0
 VUin IN VCM DC 0 SIN(0 2V 440Hz 0 0 0) AC 1 0
 VUneg VCM 0 +5V
@@ -35,13 +33,11 @@ VUpos VAP VCM +5V
 .PLOT TRAN {ib(T)} =PLOT(5) =AXIS(1) =NAME(I_B) =UNITS(A)
 .PLOT TRAN {i(R5)} =PLOT(6) =AXIS(1) =NAME(I_5) =UNITS(A)
 .PLOT TRAN {i(R4)} =PLOT(6) =AXIS(1) =NAME(I_4) =UNITS(A)
+.PLOT TRAN {2*(v(Uout)*0.663)} =PLOT(2) =AXIS(1) =NAME(Uout_buffer) =UNITS(V)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
 .TRAN 45u 100m 20m 45u
-.CONTROL
-SWEEP GAIN 0 1 0.1
-.ENDC
 
 *Global Parameters:
 .PARAM GAIN={0.5}