Library Erweiterung

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [TRI-SQR-VCO_OTA_SS.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 17:11:02 On 03.12.2025
+Finished Output Generation At 19:05:35 On 06.12.2025

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/TRI-SQR-VCO_OTA_SS.nsx

@@ -1,5 +1,5 @@
 TRI-SQR-VCO_OTA_SS
-*SPICE Netlist generated by Advanced Sim server on 03.12.2025 17:11:08
+*SPICE Netlist generated by Advanced Sim server on 06.12.2025 19:09:34
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -24,8 +24,9 @@ XICSA R.VMID NetICS_2 VAP 0 NetICS_2 LF411
 XICSB R.VMID NetICS_2 VAP 0 NetICS_2 LF411
 RR2 0 U_TRI 22k
 RR3 VAP NetIC1_1 15k
-RR4a NetIC3_2 U_TRI 100k
-RR4b U_in NetIC3_2 50k
+RR4a_p1 NetR4a_p1_1 U_TRI 20k
+RR4a_p2 NetIC3_2 NetR4a_p1_1 20k
+RR4b U_in NetIC3_2 20k
 RR_A VCM U_SQR_OTA 3.63k
 RR_CV U_CV NetIC3_9 55k
 RR_E NetC_an_2 NetR_E_2 10k
@@ -46,7 +47,7 @@ RR_SAW_b NetIC2_12 U_in 10k
 RR_SAW_c U_SAW NetIC2_13 10k
 RR_SAW_e U_SQR fet_gate 33k
 RR_SAW_f 0 fet_gate 100k
-RRoff NetIC3_2 0 250k
+RRoff NetIC3_2 0 100k
 QT1 NetC_an_1 VCM NetC_an_2 2N2907
 QT2 NetT2_3 U_C NetC_an_2 2N2907
 JT_SAW VCM fet_gate NetIC2_12 BF256B
@@ -56,18 +57,20 @@ VU_messref NetR_E_2 NetIC2_7 0
 VU_single VAP 0 +10V
 VU_var NetR_off_d_1 0 1
 
-.PLOT {V(fet_gate)} =PLOT(1) =AXIS(1)
+.PLOT TRAN {v(U_SQR)} =PLOT(1) =AXIS(1) =NAME(U_SQR) =UNITS(V)
+.PLOT TRAN {v(U_TRI)} =PLOT(2) =AXIS(1) =NAME(U_TRI) =UNITS(V)
+.PLOT TRAN {v(U_SAW)} =PLOT(3) =AXIS(1) =NAME(U_SAW) =UNITS(V)
+.PLOT TRAN {v(U_PWM)} =PLOT(4) =AXIS(1) =NAME(U_PWM) =UNITS(V)
+.PLOT TRAN {i(U_MESSITOGND)} =PLOT(5) =AXIS(1) =NAME(I_GND) =UNITS(A)
+.PLOT TRAN {p(U_single)} =PLOT(6) =AXIS(1) =NAME(P_Supply) =UNITS(W)
 
 .OPTIONS ABSTOL=1e-10 RELTOL=1e-2 VNTOL=1e-4 METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
-.AC DEC 10 1K 1G
+.TRAN 25u 20m 5m 25u
 .CONTROL
 SWEEP U_var LIST 1
 .ENDC
 
-*Global Parameters:
-.PARAM POS={0}
-
 *Models and Subcircuits:
 * A dual opamp ngspice model
 * file name: LM13700-DUAL.ckt