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2025-11-04 14:28:59 +01:00
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dev/analog/ETOTH-Log_Amp_Diode/Project Outputs for Log_Amp_Diode/Log_Amp_Diode.nsx
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@@ -1,21 +1,22 @@
Log_Amp_Diode
*SPICE Netlist generated by Advanced Sim server on 07.07.2025 12:46:41
*SPICE Netlist generated by Advanced Sim server on 19.10.2025 11:32:26
.options MixedSimGenerated
*Schematic Netlist:
DD U_out NetD_C DI_1N4001
XIC1A 0 NetD_C VCC VEE U_out TL074
RR U_in NetD_C 5k
VU_mess U_out 0 0
VV_var U_in 0 -2
VVneg 0 VEE 15
VVpos VCC 0 15
.PLOT DC {v(U_out)} =PLOT(1) =AXIS(1) =NAME(U_out) =UNITS(V)
.PLOT TRAN {i(U_mess)} =PLOT(1) =AXIS(1) =NAME(I_ABC) =UNITS(A)
*Selected Circuit Analyses:
.DC V_var -5 0 25m
.TRAN 0.1u 5u 0 0.1u
.CONTROL
SWEEP OPTION[TEMP] -10 60 10
SWEEP V_var LIST 0.25 0.5 1 2
.ENDC
*Models and Subcircuits: