Fix Expo-Amp

dev/analog/ETOTH-Log_Amp_Transistor/Project Outputs for Log_Amp_Transistor/Log_Amp_Transistor.nsx

@@ -1,27 +1,25 @@
 Log_Amp_Transistor
-*SPICE Netlist generated by Advanced Sim server on 20.10.2025 07:39:37
+*SPICE Netlist generated by Advanced Sim server on 11.11.2025 17:52:27
 .options MixedSimGenerated
 
 *Schematic Netlist:
 XIC1A 0 NetIC1_2 VCC VEE NetIC1_1 TL074
-RR1 NetIC1_1 NetR1_2 20k
+XIC1B 0 NetIC1_6 VCC VEE IN1 TL074
-RR_ref1 NetIC1_2 VEE 524.8k
+RR_1a NetR_1a_1 NetIC1_6 55.489k
-QT1a NetIC1_2 IN1 NetR1_2 2N2907
+RR_1b NetIC1_6 IN1 1k
-QT1b OUT1 0 NetR1_2 2N2907
+RR_E NetIC1_1 NetR_E_2 8k
-VU_ctrl NetU_ctrl_1 0 1V
+RR_ref NetIC1_2 VEE 500k
-VU_lol NetU_lol_1 0 18.021mV
+QT1a NetIC1_2 0 NetR_E_2 2N2907
+QT1b OUT1 IN1 NetR_E_2 2N2907
+VU_ctrl NetR_1a_1 0 1V
 VU_mess OUT1 0 0
 VVneg 0 VEE +5V
 VVpos VCC 0 +5V
-XX1 NetU_ctrl_1 NetU_lol_1 IN1 VOLTAGE_MULT
 
-.PLOT TRAN {i(U_mess)} =PLOT(1) =AXIS(1)
+.PLOT DC {i(U_mess)} =PLOT(1) =AXIS(1) =NAME(I_out (PNP)) =UNITS(A) =RGB(0, 0, 255)
 
 *Selected Circuit Analyses:
-.TRAN 0.1u 5u 0 0.1u
+.DC U_ctrl -5 5 25m
-.CONTROL
-SWEEP R1 5k 30k 5k U_ctrl LIST 0.5 1 2
-.ENDC
 
 *Models and Subcircuits:
 *TL074
@@ -75,9 +73,4 @@ VLN   0 92 DC 25
 + BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
 + CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
 
-* Voltage Miltiplier
-.subckt Voltage_Mult in1 in2 out
-E1 out 0 value={v(in1)*v(in2)}
-.ends
-
 .END

dev/analog/ETOTH-Log_Amp_Transistor/Project Outputs for Log_Amp_Transistor/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [Log_Amp_Transistor.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 15:03:22 On 07.07.2025
+Finished Output Generation At 17:29:55 On 11.11.2025