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VCO temp compensation, static Octave shift, uC Resolution compensation

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This commit is contained in:
Wendelin Waldhart
2025-12-06 16:38:20 +01:00
parent 06fa584b6d
commit 3d432392d3
201 changed files with 7456 additions and 10633 deletions
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15
dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx
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@@ -1,28 +1,25 @@
VCA_LM13700
*SPICE Netlist generated by Advanced Sim server on 04.12.2025 07:35:49
*SPICE Netlist generated by Advanced Sim server on 06.12.2025 13:42:56
.options MixedSimGenerated
*Schematic Netlist:
CC1 NetC1_1 NetC1_2 220nF
CC2 Uout NetC2_2 220nF
II_abc VCM NetI_abc_2 DC 0 PULSE(150u 0 0 4u 1u 5m 10m) AC 1 0
II_db VCM NetI_db_2 1mA
XIC1A NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
XIC1A NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 Uout
+ ExtraNet_XIC1A_9 ExtraNet_XIC1A_10 Vcc ExtraNet_XIC1A_12 ExtraNet_XIC1A_13
+ ExtraNet_XIC1A_14 ExtraNet_XIC1A_15 ExtraNet_XIC1A_16 LM13700-DUAL
XIC1C NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
XIC1C NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 Uout
+ ExtraNet_XIC1C_9 ExtraNet_XIC1C_10 Vcc ExtraNet_XIC1C_12 ExtraNet_XIC1C_13
+ ExtraNet_XIC1C_14 ExtraNet_XIC1C_15 ExtraNet_XIC1C_16 LM13700-DUAL
XIC1E NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
XIC1E NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 Uout
+ ExtraNet_XIC1E_9 ExtraNet_XIC1E_10 Vcc ExtraNet_XIC1E_12 ExtraNet_XIC1E_13
+ ExtraNet_XIC1E_14 ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
RR1 NetIC1_14 NetC1_2 3k
RR1 NetIC1_14 NetR1_2 3k
RR2 NetIC1_10 VCM 27k
RR3 NetC2_2 0 5.1k
RR4 VCM NetIC1_14 470R
RR5 VCM NetIC1_13 470R
RRc Uout 0 51k
VUin NetC1_1 VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
VUin NetR1_2 VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
VUneg VCM 0 +5V
VUpos Vcc VCM +5V