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VCA und VCF Anpassung auf 5V

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2025-10-16 10:27:46 +02:00
parent 7b45bcfa35
commit 688a381aed
461 changed files with 2695 additions and 710 deletions
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21
dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx
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@@ -1,11 +1,11 @@
VCA_LM13700
*SPICE Netlist generated by Advanced Sim server on 02.10.2025 16:16:07
*SPICE Netlist generated by Advanced Sim server on 16.10.2025 10:24:40
.options MixedSimGenerated
*Schematic Netlist:
CC1 NetC1_1 NetC1_2 220nF
CC2 Uout NetC2_2 220nF
II_abc 0 NetI_abc_2 100uA
II_abc 0 NetI_abc_2 50uA
II_db 0 NetI_db_2 1mA
XIC1A NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
+ ExtraNet_XIC1A_9 ExtraNet_XIC1A_10 Vcc ExtraNet_XIC1A_12 ExtraNet_XIC1A_13
@@ -16,23 +16,24 @@ XIC1C NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
XIC1E NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
+ ExtraNet_XIC1E_9 ExtraNet_XIC1E_10 Vcc ExtraNet_XIC1E_12 ExtraNet_XIC1E_13
+ ExtraNet_XIC1E_14 ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
RR1 NetIC1_14 NetC1_2 5k
RR2 NetIC1_10 0 100k
RR1 NetIC1_14 NetC1_2 3k
RR2 NetIC1_10 0 27k
RR3 NetC2_2 Vee 5.1k
RR4 0 NetIC1_14 470R
RR5 0 NetIC1_13 470R
RRc 0 0 5.1k
VU_mess Uout Vee 0V
RRc Uout Vee 51k
VUin NetC1_1 0 DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
VUneg 0 Vee +15V
VUpos Vcc 0 +15V
VUneg 0 Vee +5V
VUpos Vcc 0 +5V
.PLOT TRAN {v(Uin)} =PLOT(1) =AXIS(1) =NAME(Uin) =UNITS(V)
.PLOT TRAN {v(Rc)} =PLOT(2) =AXIS(1) =NAME(Uout) =UNITS(V)
.PLOT TRAN {i(U_mess)} =PLOT(3) =AXIS(1) =NAME(I_Rc) =UNITS(A)
*Selected Circuit Analyses:
.TRAN 45u 10m 0 45u
.TRAN 45u 100m 90m 45u
.CONTROL
SWEEP I_abc 0 150u 25u
.ENDC
*Models and Subcircuits:
* A dual opamp ngspice model