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Push-Pull Endstufe + Unterprojekte

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2025-10-02 20:05:15 +02:00
parent aa6fe530d6
commit 7b45bcfa35
231 changed files with 3685 additions and 22 deletions
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7
dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx
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@@ -1,5 +1,5 @@
VCA_LM13700
*SPICE Netlist generated by Advanced Sim server on 01.10.2025 15:29:07
*SPICE Netlist generated by Advanced Sim server on 02.10.2025 16:16:07
.options MixedSimGenerated
*Schematic Netlist:
@@ -21,14 +21,15 @@ RR2 NetIC1_10 0 100k
RR3 NetC2_2 Vee 5.1k
RR4 0 NetIC1_14 470R
RR5 0 NetIC1_13 470R
RRc Uout Vee 5.1k
RRc 0 0 5.1k
VU_mess Uout Vee 0V
VUin NetC1_1 0 DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
VUneg 0 Vee +15V
VUpos Vcc 0 +15V
.PLOT TRAN {v(Uin)} =PLOT(1) =AXIS(1) =NAME(Uin) =UNITS(V)
.PLOT TRAN {v(Rc)} =PLOT(2) =AXIS(1) =NAME(Uout) =UNITS(V)
.PLOT TRAN {v(Rc)/v(Uin)} =PLOT(3) =AXIS(1) =NAME(vu)
.PLOT TRAN {i(U_mess)} =PLOT(3) =AXIS(1) =NAME(I_Rc) =UNITS(A)
*Selected Circuit Analyses:
.TRAN 45u 10m 0 45u