Simulationen Analog - Altium

- V/Okt - Log-Amp Diode - Log-Amp Transistor - Tri/Squ-Wave Gen mit Log-Amp Transistor
2025-12-06 13:20:02 +00:00 · 2025-09-08 19:19:52 +02:00
parent e20aceee03
commit 7ba47a37e0
423 changed files with 54674 additions and 0 deletions
--- a/dev/analog/ETOTH-Log_Amp_Diode/Project
+++ b/dev/analog/ETOTH-Log_Amp_Diode/Project
@@ -0,0 +1,71 @@
+Log_Amp_Diode
+*SPICE Netlist generated by Advanced Sim server on 07.07.2025 12:46:41
+.options MixedSimGenerated
+
+*Schematic Netlist:
+DD U_out NetD_C DI_1N4001
+XIC1A 0 NetD_C VCC VEE U_out TL074
+RR U_in NetD_C 5k
+VV_var U_in 0 -2
+VVneg 0 VEE 15
+VVpos VCC 0 15
+
+.PLOT DC {v(U_out)} =PLOT(1) =AXIS(1) =NAME(U_out) =UNITS(V)
+
+*Selected Circuit Analyses:
+.DC V_var -5 0 25m
+.CONTROL
+SWEEP OPTION[TEMP] -10 60 10
+.ENDC
+
+*Models and Subcircuits:
+***************************************************************************************************************************************
+*SRC=1N4001;DI_1N4001;Diodes;Si;  50.0V  1.00A  3.00us   Diodes, Inc. diode
+.MODEL DI_1N4001 D  ( IS=76.9p RS=42.0m BV=50.0 IBV=5.00u
+ CJO=39.8p  M=0.333 N=1.45 TT=4.32u )
+
+*TL074
+*Quad LoNoise JFETInput OpAmp pkg:DIP14
+*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
+* Connections:
+*             Non-Inverting Input
+*             | Inverting Input
+*             | | Positive Power Supply
+*             | | | Negative Power Supply
+*             | | | | Output
+*             | | | | |
+.SUBCKT TL074 1 2 3 4 5
+C1   11 12 3.498E-12
+C2    6  7 15E-12
+DC    5 53 DX
+DE   54  5 DX
+DLP  90 91 DX
+DLN  92 90 DX
+DP    4  3 DX
+BGND 99  0 V=V(3)*.5 + V(4)*.5
+BB    7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+              I(VLP)*5E6 - I(VLN)*5E6
+GA    6  0 11 12 282.8E-6
+GCM   0  6 10 99 8.942E-9
+ISS   3 10 DC 195E-6
+HLIM 90  0 VLIM 1K
+J1   11  2 10 JX
+J2   12  1 10 JX
+R2    6  9 100E3
+RD1   4 11 3.536E3
+RD2   4 12 3.536E3
+RO1   8  5 150
+RO2   7 99 150
+RP    3  4 2.143E3
+RSS  10 99 1.026E6
+VB    9  0 DC 0
+VC    3 53 DC 2.2
+VE   54  4 DC 2.2
+VLIM  7  8 DC 0
+VLP  91  0 DC 25
+VLN   0 92 DC 25
+.MODEL DX D(IS=800E-18)
+.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
+.ENDS TL074
+
+.END
--- a/dev/analog/ETOTH-Log_Amp_Diode/Project
+++ b/dev/analog/ETOTH-Log_Amp_Diode/Project
@@ -0,0 +1,10 @@
+Output: Mixed Sim
+Type  : AdvSimNetlist
+From  : Project [Log_Amp_Diode.PrjPcb]
+   Generated File[Log_Amp_Diode.nsx]
+
+
+Files Generated   : 1
+Documents Printed : 0
+
+Finished Output Generation At 12:34:57 On 07.07.2025