mirror of
https://github.com/erik-toth/audio-synth.git
synced 2025-12-06 07:20:02 +00:00
Schematic + Code Updates
- ESP32-S3 Komplett - MC4728 Komplett + Test Skript
This commit is contained in:
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,5 +1,5 @@
|
||||
TRI-SQR-VCO_OTA
|
||||
*SPICE Netlist generated by Advanced Sim server on 01.10.2025 19:12:54
|
||||
*SPICE Netlist generated by Advanced Sim server on 08.10.2025 17:40:24
|
||||
.options MixedSimGenerated
|
||||
|
||||
*Schematic Netlist:
|
||||
@@ -44,16 +44,18 @@ RRoff NetIC3_2 Vee 650k
|
||||
QT1 NetC_an_1 0 NetC_an_2 2N2907
|
||||
QT2 NetT2_3 U_C NetC_an_2 2N2907
|
||||
JT_SAW 0 NetR_SAW_e_2 NetIC2_12 BF545B
|
||||
VU_I-GND-MESS NetU_I-GND-MESS_1 0 0
|
||||
VU_mess NetT2_3 NetIC1_16 0
|
||||
VU_messref NetR_E_2 NetIC2_7 0
|
||||
VU_neg 0 Vee 15
|
||||
VU_pos Vcc 0 15
|
||||
VU_neg NetU_I-GND-MESS_1 Vee 15
|
||||
VU_pos Vcc NetU_I-GND-MESS_1 15
|
||||
VU_var NetR_CV_1 0 1
|
||||
|
||||
.PLOT TRAN {v(U_SQR)} =PLOT(2) =AXIS(1) =NAME(U_SQR) =UNITS(V)
|
||||
.PLOT TRAN {v(U_TRI)} =PLOT(1) =AXIS(1) =NAME(U_TRI) =UNITS(V)
|
||||
.PLOT TRAN {v(U_SAW)} =PLOT(3) =AXIS(1) =NAME(U_SAW) =UNITS(V)
|
||||
.PLOT TRAN {v(U_PWM)} =PLOT(4) =AXIS(1) =NAME(PWM) =UNITS(V)
|
||||
.PLOT TRAN {i(U_I-GND-MESS)} =PLOT(5) =AXIS(1) =NAME(I_GND) =UNITS(A)
|
||||
|
||||
.OPTIONS ITL4=100 METHOD=GEAR MAXORD=2
|
||||
*Selected Circuit Analyses:
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
Reference in New Issue
Block a user