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VCA --> MCU einbindung

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@Wendl TODO
This commit is contained in:
Erik Tóth
2025-12-04 07:46:28 +01:00
parent c5da67e7de
commit 7ca3d9e5e1
215 changed files with 5779 additions and 3319 deletions
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38
dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/ETOTH-Amp_LM386.nsx
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@@ -1,27 +1,31 @@
ETOTH-Amp_LM386
*SPICE Netlist generated by Advanced Sim server on 28.11.2025 11:11:11
*SPICE Netlist generated by Advanced Sim server on 03.12.2025 21:51:07
.options MixedSimGenerated
*Schematic Netlist:
CC_DCBLOCK_IN IN NetC_DCBLOCK_IN_2 10uF
CC_DCBLOCK_IN NetC_DCBLOCK_IN_1 IN_FILT 10uF
CC_DCBLOCK_OUT NetC_DCBLOCK_OUT_1 OUT 220uF
XIC1A NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386
XIC1B NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386
LL_Speaker 0 NetL_Speaker_2 0.1mH
RR_G NetR_G_1 NetR_G_2 100k
RR_POTA 0 NetR_POT_2 {10k * {POS}}
RR_POTB NetR_POT_2 NetC_DCBLOCK_IN_2 {10k - (10k * {POS})}
RR_Speaker NetL_Speaker_2 OUT 8R
RR_POTB NetR_POT_2 IN_FILT {10k - (10k * {POS})}
RR_Speaker NetL_Speaker_2 OUT 4R
RR_static1 NetIC1_3 NetR_POT_2 100k
RR_static2 0 NetIC1_3 10k
XT1 NetR_G_2 IN NetC_DCBLOCK_IN_1 BUZ-81
VU_KBactive NetR_G_1 0 DC 0 PULSE(3.3 0 0 4u 1u 4.5m*4 4.5m*8) AC 1 0
VU_q VAP 0 10V
VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255)
.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
.PLOT TRAN {v(U_KBactive)} =PLOT(2) =AXIS(1) =NAME(U_KBactive) =UNITS(V)
.OPTIONS METHOD=GEAR MAXORD=2
*Selected Circuit Analyses:
.TRAN 90.91u 22.73m 0 90.91u
.TRAN 90.91u 180.0m 0 90.91u
*Global Parameters:
.PARAM POS={1}
@@ -108,4 +112,28 @@ q14 out 10018 gnd ddnpn 100
+ Tf=1n Itf=1 Xtf=0 Vtf=10)
.ends LM386
*******
*SRC=BUZ-81;BUZ-81;MOSFETs N;Siemens;800V 4A 2.5 Ohm
*SYM=N-MOSFET
.SUBCKT BUZ-81 1 2 3
LS 5 2 7N
LD 95 3 5N
RG 4 11 5.5M
RS 5 76 23M
D81 76 95 DREV
.MODEL DREV D CJO=0.4N RS=20M TT=625N IS=300P BV=800
M81 86 11 76 96 MBUZ
.MODEL MBUZ NMOS VTO=3.463 KP=3.263
M2 11 86 8 8 MSW
.MODEL MSW NMOS VTO=0.001 KP=5
M3 86 11 8 8 MSW
COX 11 8 1.3N
DGD 8 86 DCGD
.MODEL DCGD D CJO=0.265N M=0.495 VJ=0.975
CGS 76 11 1N
MRDR 86 86 95 86 MVRD
.MODEL MVRD NMOS VTO=-24.99 KP=.022
LG 4 1 7N
.ENDS
.END

2
dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/Status Report.Txt
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@@ -7,4 +7,4 @@ From : Project [ETOTH-Amp_LM386.PrjPcb]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 11:00:20 On 28.11.2025
Finished Output Generation At 20:19:33 On 03.12.2025