mirror of
https://github.com/erik-toth/audio-synth.git
synced 2025-12-06 11:20:02 +00:00
VCA --> MCU einbindung
@Wendl TODO
This commit is contained in:
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@@ -7,4 +7,4 @@ From : Project [TRI-SQR-VCO_OTA_SS.PrjPcb]
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Files Generated : 1
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Documents Printed : 0
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Finished Output Generation At 12:23:27 On 28.11.2025
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Finished Output Generation At 17:11:02 On 03.12.2025
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@@ -1,5 +1,5 @@
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TRI-SQR-VCO_OTA_SS
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*SPICE Netlist generated by Advanced Sim server on 02.12.2025 15:10:05
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*SPICE Netlist generated by Advanced Sim server on 03.12.2025 17:11:08
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.options MixedSimGenerated
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*Schematic Netlist:
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@@ -56,24 +56,118 @@ VU_messref NetR_E_2 NetIC2_7 0
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VU_single VAP 0 +10V
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VU_var NetR_off_d_1 0 1
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.PLOT TRAN {v(U_SQR)} =PLOT(1) =AXIS(1) =NAME(U_SQR) =UNITS(V)
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.PLOT TRAN {v(U_TRI)} =PLOT(2) =AXIS(1) =NAME(U_TRI) =UNITS(V)
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.PLOT TRAN {v(U_SAW)} =PLOT(3) =AXIS(1) =NAME(U_SAW) =UNITS(V)
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.PLOT TRAN {v(U_PWM)} =PLOT(4) =AXIS(1) =NAME(U_PWM) =UNITS(V)
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.PLOT TRAN {v(U_C)} =PLOT(5) =AXIS(1) =NAME(Uc) =UNITS(V)
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.PLOT TRAN {i(U_mess)} =PLOT(6) =AXIS(1) =NAME(i_abc) =UNITS(A)
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.PLOT {V(fet_gate)} =PLOT(1) =AXIS(1)
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.OPTIONS ABSTOL=1e-10 RELTOL=1e-2 VNTOL=1e-4 METHOD=GEAR MAXORD=2
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*Selected Circuit Analyses:
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.TRAN 10u 20m 5m 10u
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.AC DEC 10 1K 1G
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.CONTROL
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SWEEP U_var LIST 1
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.ENDC
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*Global Parameters:
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.PARAM POS=0
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.PARAM POS={0}
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*Models and Subcircuits:
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* A dual opamp ngspice model
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* file name: LM13700-DUAL.ckt
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.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
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+ 2out 2in- 2in+ 2Dbias 2ABin
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*//////////////////////////////////////////////////////////////////////
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* (C) National Semiconductor, Inc.
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* Models developed and under copyright by:
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* National Semiconductor, Inc.
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*/////////////////////////////////////////////////////////////////////
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* Legal Notice: This material is intended for free software support.
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* The file may be copied, and distributed; however, reselling the
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* material is illegal
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*////////////////////////////////////////////////////////////////////
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* For ordering or technical information on these models, contact:
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* National Semiconductor's Customer Response Center
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* 7:00 A.M.--7:00 P.M. U.S. Central Time
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* (800) 272-9959
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* For Applications support, contact the Internet address:
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* amps-apps@galaxy.nsc.com
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* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
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* LM13700 Dual Operational Transconductance Amplifier
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* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
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*
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* Amplifier Bias Input
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* | Diode Bias
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* | | Positive Input
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* | | | Negative Input
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* | | | | Output
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* | | | | | Negative power supply
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* | | | | | | Buffer Input
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* | | | | | | | Buffer Output
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* | | | | | | | | Positive power supply
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* | | | | | | | | |
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.SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11
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*
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* Features:
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* gm adjustable over 6 decades.
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* Excellent gm linearity.
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* Linearizing diodes.
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* Wide supply range of +/-2V to +/-22V.
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*
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* Note: This model is single-pole in nature and over-estimates
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* AC bandwidth and phase margin (stability) by over 2X.
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* Although refinement may be possible in the future, please
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* use benchtesting to finalize AC circuit design.
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*
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* Note: Model is for single device only and simulated
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* supply current is 1/2 of total device current.
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*
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******************************************************
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*
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C1 6 4 4.8P
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C2 3 6 4.8P
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* Output capacitor
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C3 5 6 6.26P
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D1 2 4 DX
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D2 2 3 DX
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D3 11 21 DX
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D4 21 22 DX
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D5 1 26 DX
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D6 26 27 DX
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D7 5 29 DX
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D8 28 5 DX
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D10 31 25 DX
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* Clamp for -CMR
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D11 28 25 DX
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* Ios source
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F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9
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F2 11 5 V2 1.022
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F3 25 6 V3 1.0
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F4 5 6 V1 1.022
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* Output impedance
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F5 5 0 POLY(2) V3 V7 0 0 0 0 1
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G1 0 33 5 0 .55E-3
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I1 11 6 300U
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Q1 24 32 31 QX1
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Q2 23 3 31 QX2
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Q3 11 7 30 QZ
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Q4 11 30 8 QY
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V1 22 24 0V
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V2 22 23 0V
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V3 27 6 0V
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V4 11 29 1.4
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V5 28 6 1.2
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V6 4 32 0V
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V7 33 0 0V
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.MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
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.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
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.MODEL QY NPN (IS=6E-15 BF=50)
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.MODEL QZ NPN (IS=5E-16 BF=266)
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.MODEL DX D (IS=5E-16)
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.ENDS
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*$
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XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
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XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
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.ends
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*TL074
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*Quad LoNoise JFETInput OpAmp pkg:DIP14
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*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
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@@ -241,104 +335,4 @@ D3 15 24 DX
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+ FC = 5.00000E-001
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+)
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*Cached Models and Subcircuits:
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* A dual opamp ngspice model
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* file name: LM13700-DUAL.ckt
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.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
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+ 2out 2in- 2in+ 2Dbias 2ABin
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*//////////////////////////////////////////////////////////////////////
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* (C) National Semiconductor, Inc.
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* Models developed and under copyright by:
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* National Semiconductor, Inc.
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*/////////////////////////////////////////////////////////////////////
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* Legal Notice: This material is intended for free software support.
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* The file may be copied, and distributed; however, reselling the
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* material is illegal
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*////////////////////////////////////////////////////////////////////
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* For ordering or technical information on these models, contact:
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* National Semiconductor's Customer Response Center
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* 7:00 A.M.--7:00 P.M. U.S. Central Time
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* (800) 272-9959
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* For Applications support, contact the Internet address:
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* amps-apps@galaxy.nsc.com
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* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
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* LM13700 Dual Operational Transconductance Amplifier
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* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
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*
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* Amplifier Bias Input
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* | Diode Bias
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* | | Positive Input
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* | | | Negative Input
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* | | | | Output
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* | | | | | Negative power supply
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* | | | | | | Buffer Input
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* | | | | | | | Buffer Output
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* | | | | | | | | Positive power supply
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* | | | | | | | | |
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.SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11
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*
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* Features:
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* gm adjustable over 6 decades.
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* Excellent gm linearity.
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* Linearizing diodes.
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* Wide supply range of +/-2V to +/-22V.
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*
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* Note: This model is single-pole in nature and over-estimates
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* AC bandwidth and phase margin (stability) by over 2X.
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* Although refinement may be possible in the future, please
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* use benchtesting to finalize AC circuit design.
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*
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* Note: Model is for single device only and simulated
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* supply current is 1/2 of total device current.
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*
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******************************************************
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*
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C1 6 4 4.8P
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C2 3 6 4.8P
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* Output capacitor
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C3 5 6 6.26P
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D1 2 4 DX
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D2 2 3 DX
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D3 11 21 DX
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D4 21 22 DX
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D5 1 26 DX
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D6 26 27 DX
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D7 5 29 DX
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D8 28 5 DX
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D10 31 25 DX
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* Clamp for -CMR
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D11 28 25 DX
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* Ios source
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F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9
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F2 11 5 V2 1.022
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F3 25 6 V3 1.0
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F4 5 6 V1 1.022
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* Output impedance
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F5 5 0 POLY(2) V3 V7 0 0 0 0 1
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G1 0 33 5 0 .55E-3
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I1 11 6 300U
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Q1 24 32 31 QX1
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Q2 23 3 31 QX2
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Q3 11 7 30 QZ
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Q4 11 30 8 QY
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V1 22 24 0V
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V2 22 23 0V
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V3 27 6 0V
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V4 11 29 1.4
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V5 28 6 1.2
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V6 4 32 0V
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V7 33 0 0V
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.MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
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.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
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.MODEL QY NPN (IS=6E-15 BF=50)
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.MODEL QZ NPN (IS=5E-16 BF=266)
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.MODEL DX D (IS=5E-16)
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.ENDS
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*$
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XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
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XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
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.ends
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.END
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