VCA --> MCU einbindung

@Wendl TODO

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/Status Report.Txt

@@ -0,0 +1,10 @@
+Output: Mixed Sim
+Type  : AdvSimNetlist
+From  : Project [VCA_LM13700.PrjPcb]
+   Generated File[VCA_LM13700.nsx]
+
+
+Files Generated   : 1
+Documents Printed : 0
+
+Finished Output Generation At 07:30:33 On 04.12.2025

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx

@@ -1,30 +1,30 @@
 VCA_LM13700
-*SPICE Netlist generated by Advanced Sim server on 16.10.2025 10:24:40
+*SPICE Netlist generated by Advanced Sim server on 04.12.2025 07:35:49
 .options MixedSimGenerated
 
 *Schematic Netlist:
 CC1 NetC1_1 NetC1_2 220nF
 CC2 Uout NetC2_2 220nF
-II_abc 0 NetI_abc_2 50uA
-II_db 0 NetI_db_2 1mA
-XIC1A NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
+II_abc VCM NetI_abc_2 DC 0 PULSE(150u 0 0 4u 1u 5m 10m) AC 1 0
+II_db VCM NetI_db_2 1mA
+XIC1A NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
 + ExtraNet_XIC1A_9 ExtraNet_XIC1A_10 Vcc ExtraNet_XIC1A_12 ExtraNet_XIC1A_13
 + ExtraNet_XIC1A_14 ExtraNet_XIC1A_15 ExtraNet_XIC1A_16 LM13700-DUAL
-XIC1C NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
+XIC1C NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
 + ExtraNet_XIC1C_9 ExtraNet_XIC1C_10 Vcc ExtraNet_XIC1C_12 ExtraNet_XIC1C_13
 + ExtraNet_XIC1C_14 ExtraNet_XIC1C_15 ExtraNet_XIC1C_16 LM13700-DUAL
-XIC1E NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
+XIC1E NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
 + ExtraNet_XIC1E_9 ExtraNet_XIC1E_10 Vcc ExtraNet_XIC1E_12 ExtraNet_XIC1E_13
 + ExtraNet_XIC1E_14 ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
 RR1 NetIC1_14 NetC1_2 3k
-RR2 NetIC1_10 0 27k
-RR3 NetC2_2 Vee 5.1k
-RR4 0 NetIC1_14 470R
-RR5 0 NetIC1_13 470R
-RRc Uout Vee 51k
-VUin NetC1_1 0 DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
-VUneg 0 Vee +5V
-VUpos Vcc 0 +5V
+RR2 NetIC1_10 VCM 27k
+RR3 NetC2_2 0 5.1k
+RR4 VCM NetIC1_14 470R
+RR5 VCM NetIC1_13 470R
+RRc Uout 0 51k
+VUin NetC1_1 VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
+VUneg VCM 0 +5V
+VUpos Vcc VCM +5V
 
 .PLOT TRAN {v(Uin)} =PLOT(1) =AXIS(1) =NAME(Uin) =UNITS(V)
 .PLOT TRAN {v(Rc)} =PLOT(2) =AXIS(1) =NAME(Uout) =UNITS(V)
@@ -32,7 +32,6 @@ VUpos Vcc 0 +5V
 *Selected Circuit Analyses:
 .TRAN 45u 100m 90m 45u
 .CONTROL
-SWEEP I_abc 0 150u 25u
 .ENDC
 
 *Models and Subcircuits: