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VCA --> MCU einbindung
@Wendl TODO
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@@ -1,30 +1,30 @@
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VCA_LM13700
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*SPICE Netlist generated by Advanced Sim server on 16.10.2025 10:24:40
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*SPICE Netlist generated by Advanced Sim server on 04.12.2025 07:35:49
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.options MixedSimGenerated
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*Schematic Netlist:
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CC1 NetC1_1 NetC1_2 220nF
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CC2 Uout NetC2_2 220nF
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II_abc 0 NetI_abc_2 50uA
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II_db 0 NetI_db_2 1mA
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XIC1A NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
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II_abc VCM NetI_abc_2 DC 0 PULSE(150u 0 0 4u 1u 5m 10m) AC 1 0
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II_db VCM NetI_db_2 1mA
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XIC1A NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
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+ ExtraNet_XIC1A_9 ExtraNet_XIC1A_10 Vcc ExtraNet_XIC1A_12 ExtraNet_XIC1A_13
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+ ExtraNet_XIC1A_14 ExtraNet_XIC1A_15 ExtraNet_XIC1A_16 LM13700-DUAL
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XIC1C NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
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XIC1C NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
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+ ExtraNet_XIC1C_9 ExtraNet_XIC1C_10 Vcc ExtraNet_XIC1C_12 ExtraNet_XIC1C_13
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+ ExtraNet_XIC1C_14 ExtraNet_XIC1C_15 ExtraNet_XIC1C_16 LM13700-DUAL
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XIC1E NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 Vee NetIC1_10 NetC2_2
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XIC1E NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
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+ ExtraNet_XIC1E_9 ExtraNet_XIC1E_10 Vcc ExtraNet_XIC1E_12 ExtraNet_XIC1E_13
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+ ExtraNet_XIC1E_14 ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
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RR1 NetIC1_14 NetC1_2 3k
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RR2 NetIC1_10 0 27k
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RR3 NetC2_2 Vee 5.1k
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RR4 0 NetIC1_14 470R
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RR5 0 NetIC1_13 470R
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RRc Uout Vee 51k
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VUin NetC1_1 0 DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
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VUneg 0 Vee +5V
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VUpos Vcc 0 +5V
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RR2 NetIC1_10 VCM 27k
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RR3 NetC2_2 0 5.1k
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RR4 VCM NetIC1_14 470R
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RR5 VCM NetIC1_13 470R
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RRc Uout 0 51k
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VUin NetC1_1 VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
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VUneg VCM 0 +5V
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VUpos Vcc VCM +5V
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.PLOT TRAN {v(Uin)} =PLOT(1) =AXIS(1) =NAME(Uin) =UNITS(V)
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.PLOT TRAN {v(Rc)} =PLOT(2) =AXIS(1) =NAME(Uout) =UNITS(V)
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@@ -32,7 +32,6 @@ VUpos Vcc 0 +5V
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*Selected Circuit Analyses:
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.TRAN 45u 100m 90m 45u
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.CONTROL
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SWEEP I_abc 0 150u 25u
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.ENDC
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*Models and Subcircuits:
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