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This commit is contained in:
Wendelin Waldhart
2026-03-24 20:32:47 +01:00
parent 32332f65cc
commit 802001217d
799 changed files with 166608 additions and 13302 deletions
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34
dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx
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@@ -1,5 +1,5 @@
VCA_LM13700
*SPICE Netlist generated by Advanced Sim server on 06.02.2026 11:37:11
*SPICE Netlist generated by Advanced Sim server on 24.03.2026 11:45:11
.options MixedSimGenerated
*Schematic Netlist:
@@ -13,38 +13,38 @@ XIC1E NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1E_9
+ ExtraNet_XIC1E_10 VAP ExtraNet_XIC1E_12 ExtraNet_XIC1E_13 ExtraNet_XIC1E_14
+ ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
RR1 NetIC1_14 IN 3.3k
RR2a OUT NetR2a_2 20k
RR2b NetR2a_2 VCM 6.8k
RR3 Uout 0 5.1k
RR4 VCM NetIC1_14 1.2k
RR5 VCM NetIC1_13 1.2k
RR_B NetR_B_1 NetR_B_2 100k
RR_BASE_GAIN NetIC1_16 NetR_BASE_GAIN_2 10k
RR_B NetR_B_1 U_Enable 100k
RR_BASE_GAIN NetR_BASE_GAIN_1 NetIC1_16 10k
RR_D VAP NetIC1_15 5.1k
RR_GAINA NetR_BASE_GAIN_2 NetR_BASE_GAIN_2 {100k * {GAIN}}
RR_GAINB NetR_BASE_GAIN_2 U_ABC {100k - (100k * {GAIN})}
QT VAP NetR_B_1 U_ABC QBC547B
VU_VCO_EN NetR_B_2 0 DC 0 PULSE(3.3 0 0 4u 1u 20m 40m) AC 1 0
VUin IN VCM DC 0 SIN(0 0 440Hz 0 0 0) AC 1 0
RR_GAINA NetR_BASE_GAIN_1 NetR_GAIN_2 {100k * {GAIN}}
RR_GAINB NetR_GAIN_2 NetR_GAIN_2 {100k - (100k * {GAIN})}
RRv_a OUT NetRv_a_2 18k
RRv_b NetRv_a_2 VCM 6.8k
QT VAP NetR_B_1 NetR_GAIN_2 QBC547B
VU_VCO_EN U_Enable 0 DC 0 PULSE(3.3 0 0 4u 1u 20m 40m) AC 1 0
VUin IN VCM DC 0 SIN(0 1V 440Hz 0 0 0) AC 1 0
VUneg VCM 0 +5V
VUpos VAP VCM +5V
.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(Uin) =UNITS(V)
.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(Uout) =UNITS(V)
.PLOT TRAN {v(U_VCO_EN)} =PLOT(3) =AXIS(1) =NAME(VCO_EN) =UNITS(V)
.PLOT TRAN {ie(T)} =PLOT(4) =AXIS(1) =NAME(I_ABC) =UNITS(A)
.PLOT TRAN {ib(T)} =PLOT(5) =AXIS(1) =NAME(I_B) =UNITS(A)
.PLOT TRAN {i(R5)} =PLOT(6) =AXIS(1) =NAME(I_5) =UNITS(A)
.PLOT TRAN {i(R4)} =PLOT(6) =AXIS(1) =NAME(I_4) =UNITS(A)
.PLOT TRAN {i(R_BASE_GAIN)} =PLOT(6) =AXIS(1) =NAME(I_ABC) =UNITS(A)
.PLOT TRAN {i(R5)} =PLOT(4) =AXIS(1) =NAME(I_5) =UNITS(A)
.PLOT TRAN {i(R4)} =PLOT(4) =AXIS(1) =NAME(I_4) =UNITS(A)
.PLOT TRAN {2*(v(Uout)*0.663)} =PLOT(2) =AXIS(1) =NAME(Uout_buffer) =UNITS(V)
.PLOT TRAN {v(U_ABC)} =PLOT(7) =AXIS(1) =NAME(U_ABC) =UNITS(V)
.PLOT TRAN {v(VAP)-v(U_ABC)} =PLOT(5) =AXIS(1) =NAME(U_ABC) =UNITS(V)
.PLOT TRAN {i(R_D)} =PLOT(5) =AXIS(1) =NAME(I_D) =UNITS(A) =RGB(126, 88, 219)
.OPTIONS METHOD=GEAR MAXORD=2
*Selected Circuit Analyses:
.TRAN 45u 100m 20m 45u
.TRAN 45u 50m 30m 45u
*Global Parameters:
.PARAM GAIN={0.5}
.PARAM GAIN=0
*Models and Subcircuits:
* A dual opamp ngspice model