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VCF added HP, small circuit changes, changed controll current

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This commit is contained in:
Wendelin Waldhart
2025-12-22 13:07:24 +01:00
parent d7025a91f9
commit 9798c31663
29 changed files with 2401 additions and 11 deletions
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dev/analog/Filter_Test/Filter_Test.PrjPcb Normal file
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Record=TopLevelDocument|FileName=Filter_Test.SchDoc|SheetNumber=1

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dev/analog/Filter_Test/Project Logs for Filter_Test/Filter_Test SCH ECO 21.12.2025 10-48-24.LOG Normal file
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Change Component Designator: Old Designator=C? New Designator=C1
Change Component Designator: Old Designator=R? New Designator=R1
Change Component Designator: Old Designator=R? New Designator=R2
Change Component Designator: Old Designator=R? New Designator=R3
Change Component Designator: Old Designator=R? New Designator=R4
Change Component Designator: Old Designator=R? New Designator=R5

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dev/analog/Filter_Test/Project Logs for Filter_Test/Filter_Test SCH ECO 21.12.2025 20-28-28.LOG Normal file
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Change Component Designator: Old Designator=C? New Designator=C3
Change Component Designator: Old Designator=R? New Designator=R10
Change Component Designator: Old Designator=R? New Designator=R11
Change Component Designator: Old Designator=R? New Designator=R12
Change Component Designator: Old Designator=R? New Designator=R13
Change Component Designator: Old Designator=R? New Designator=R14
Change Component Designator: Old Designator=R? New Designator=R15

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dev/analog/Filter_Test/Project Outputs for Filter_Test/Filter_Test.nsx Normal file
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Filter_Test
*SPICE Netlist generated by Advanced Sim server on 21.12.2025 21:14:32
.options MixedSimGenerated
*Schematic Netlist:
CC1 NetC1_1 VCM 1nF
CC2 VCM NetC2_2 1nF
CC3 Uin NetC3_2 150pF
XIC1A NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 NetC1_1 0 NetC1_1 BP LP NetC2_2 VAP
+ NetC2_2 VCM NetIC1_3 NetIC1_2 NetIC1_1 LM13700-DUAL
XIC1B NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 NetC1_1 0 NetC1_1 BP LP NetC2_2 VAP
+ NetC2_2 VCM NetIC1_3 NetIC1_2 NetIC1_1 LM13700-DUAL
XIC1C NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 NetC1_1 0 NetC1_1 BP LP NetC2_2 VAP
+ NetC2_2 VCM NetIC1_3 NetIC1_2 NetIC1_1 LM13700-DUAL
XIC1D NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 NetC1_1 0 NetC1_1 BP LP NetC2_2 VAP
+ NetC2_2 VCM NetIC1_3 NetIC1_2 NetIC1_1 LM13700-DUAL
XIC1E NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 NetC1_1 0 NetC1_1 BP LP NetC2_2 VAP
+ NetC2_2 VCM NetIC1_3 NetIC1_2 NetIC1_1 LM13700-DUAL
XIC2A VCM NetIC2_2 VAP 0 NetIC2_1 TL074
XIC3A NetIC3_16 NetIC3_15 NetIC3_14 NetIC3_13 NetC3_2 0 NetC3_2 HP
+ ExtraNet_XIC3A_9 ExtraNet_XIC3A_10 VAP ExtraNet_XIC3A_12 ExtraNet_XIC3A_13
+ ExtraNet_XIC3A_14 ExtraNet_XIC3A_15 ExtraNet_XIC3A_16 LM13700-DUAL
XIC3C NetIC3_16 NetIC3_15 NetIC3_14 NetIC3_13 NetC3_2 0 NetC3_2 HP
+ ExtraNet_XIC3C_9 ExtraNet_XIC3C_10 VAP ExtraNet_XIC3C_12 ExtraNet_XIC3C_13
+ ExtraNet_XIC3C_14 ExtraNet_XIC3C_15 ExtraNet_XIC3C_16 LM13700-DUAL
XIC3E NetIC3_16 NetIC3_15 NetIC3_14 NetIC3_13 NetC3_2 0 NetC3_2 HP
+ ExtraNet_XIC3E_9 ExtraNet_XIC3E_10 VAP ExtraNet_XIC3E_12 ExtraNet_XIC3E_13
+ ExtraNet_XIC3E_14 ExtraNet_XIC3E_15 ExtraNet_XIC3E_16 LM13700-DUAL
RR1 Uin NetIC1_14 10k
RR2 VCM NetIC1_14 1k
RR3 BP NetIC1_13 10k
RR4 NetIC1_13 VCM 1k
RR5 0 BP 5.6k
RR6 0 LP 5.6k
RR7 LP NetIC1_13 10k
RR8 BP NetIC1_3 33k
RR9 NetIC1_3 VCM 1k
RR11 NetIC3_14 VAP 330k
RR12 NetIC3_14 VCM 1k
RR13 NetIC3_13 HP 100k
RR14 NetIC3_13 VCM 1k
RR15 0 HP 10k
RR_abcA NetIC2_1 NetR_abc_2 {1Meg * {Q}}
RR_abcB NetR_abc_2 NetR_abc_2 {1Meg - (1Meg * {Q})}
RR_abc_1 VAP div 100k
RR_abc_2 div NetR_abc_2_2 22k
RR_abc_3 NetR_abc_2_2 VCM 3.3k
RR_hilfe div NetIC2_2 1k
RR_hilfe2 NetIC2_2 NetIC2_1 100k
VU_mess_abc NetIC3_16 NetR_abc_2 0
VU_mess_abc1 NetIC1_16 NetR_abc_2 0
VU_mess_abc2 NetIC1_1 NetR_abc_2 0
VUe Uin VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
VUneg VCM 0 +5V
VUpos VAP VCM +5V
.PLOT AC {dB(v(BP))} =PLOT(1) =AXIS(1) =NAME(Au_Uout) =UNITS(dB)
.PLOT AC {dB(v(LP))} =PLOT(2) =AXIS(1) =NAME(Au_Uout2) =UNITS(dB)
.PLOT AC {dB(v(HP))} =PLOT(3) =AXIS(1) =NAME(Au_HP) =UNITS(dB)
*Selected Circuit Analyses:
.AC DEC 50 20 20k
.CONTROL
SWEEP Q LIST 0.002 0.01 0.1 1
.ENDC
*Global Parameters:
.PARAM Q=0.1
*Models and Subcircuits:
* A dual opamp ngspice model
* file name: LM13700-DUAL.ckt
.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
+ 2out 2in- 2in+ 2Dbias 2ABin
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
* LM13700 Dual Operational Transconductance Amplifier
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
*
* Amplifier Bias Input
* | Diode Bias
* | | Positive Input
* | | | Negative Input
* | | | | Output
* | | | | | Negative power supply
* | | | | | | Buffer Input
* | | | | | | | Buffer Output
* | | | | | | | | Positive power supply
* | | | | | | | | |
.SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11
*
* Features:
* gm adjustable over 6 decades.
* Excellent gm linearity.
* Linearizing diodes.
* Wide supply range of +/-2V to +/-22V.
*
* Note: This model is single-pole in nature and over-estimates
* AC bandwidth and phase margin (stability) by over 2X.
* Although refinement may be possible in the future, please
* use benchtesting to finalize AC circuit design.
*
* Note: Model is for single device only and simulated
* supply current is 1/2 of total device current.
*
******************************************************
*
C1 6 4 4.8P
C2 3 6 4.8P
* Output capacitor
C3 5 6 6.26P
D1 2 4 DX
D2 2 3 DX
D3 11 21 DX
D4 21 22 DX
D5 1 26 DX
D6 26 27 DX
D7 5 29 DX
D8 28 5 DX
D10 31 25 DX
* Clamp for -CMR
D11 28 25 DX
* Ios source
F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9
F2 11 5 V2 1.022
F3 25 6 V3 1.0
F4 5 6 V1 1.022
* Output impedance
F5 5 0 POLY(2) V3 V7 0 0 0 0 1
G1 0 33 5 0 .55E-3
I1 11 6 300U
Q1 24 32 31 QX1
Q2 23 3 31 QX2
Q3 11 7 30 QZ
Q4 11 30 8 QY
V1 22 24 0V
V2 22 23 0V
V3 27 6 0V
V4 11 29 1.4
V5 28 6 1.2
V6 4 32 0V
V7 33 0 0V
.MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QY NPN (IS=6E-15 BF=50)
.MODEL QZ NPN (IS=5E-16 BF=266)
.MODEL DX D (IS=5E-16)
.ENDS
*$
XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
.ends
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
.END

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dev/analog/Filter_Test/Simulation/Filter_Test.sdf Normal file
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ChartId: QUFLUHPB
ChartView: 4
ChartTitle: AC Analysis
ChartBackgroundColor: 16777215
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ChartXOffset: 0.00000000000000E+000
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ChartXScaleLogBase: 10
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ChartBoldWaves: TRUE
ChartHighlightSimilarWaves: TRUE
ChartShowDataPoints: FALSE
ChartShowWaveSymbols: FALSE
ChartShowChartTitle: TRUE
ChartShowPlotTitle: TRUE
ChartShowAxisLabels: TRUE
ChartSimDataPanel: FALSE
ChartZoomPlotsSeparately: TRUE
ChartFFTLength: 128
ChartDisplayMeasurements: FALSE
ChartCursorDisplay_AcRms: FALSE
ChartCursorDisplay_RMS: FALSE
ChartCursorDisplay_Average: FALSE
ChartCursorDisplay_BminusA: FALSE
ChartCursorDisplay_Frequency: FALSE
ChartCursorDisplay_Maximum: FALSE
ChartCursorDisplay_Minimum: FALSE
ChartCursorDisplay_RMS: FALSE
ChartCursorDisplay_XY: TRUE
ChartFourier: FALSE
ChartTable: FALSE
ChartType: XY Scatter
ChartXUnitStr: Hz
ChartXLabel: Frequency
ChartRelatedChartId:
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CellHeight: 520
CellIsScaled: TRUE
CellIsDigital: FALSE
CellIsPartial: FALSE
CellTitle
CellXGrid: TRUE
CellYGrid: TRUE
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CellAxisDivisions: 8
CellAxisLabel:
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CellAxisAutoDiv: TRUE
CellAxisAutoUnits: TRUE
CellAxisDivSize: 1.00000000000000E+001
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WaveIsXComplex: TRUE
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WaveYUnitStr: Hz
WaveHint: Q = 0.1
WavePoints: 151
WaveIsXComplex: TRUE
WaveIsYComplex: TRUE
WaveType: 0
WaveVariableType: General
WaveSuffix: _p3
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WaveIsXComplex: TRUE
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WaveType: 0
WaveVariableType: General
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WaveYUnitStr: Hz
WaveHint: Q = 1
WavePoints: 151
WaveIsXComplex: TRUE
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WaveType: 0
WaveVariableType: General
WaveSuffix: _p4
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WaveHint: Q = 1
WavePoints: 151
WaveIsXComplex: TRUE
WaveIsYComplex: TRUE
WaveType: 0
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WaveSuffix: _p4
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@@ -1,5 +1,5 @@
VCF_LM13700_StateVariable VCF_LM13700_StateVariable
*SPICE Netlist generated by Advanced Sim server on 18.11.2025 17:07:57 *SPICE Netlist generated by Advanced Sim server on 21.12.2025 11:31:08
.options MixedSimGenerated .options MixedSimGenerated
*Schematic Netlist: *Schematic Netlist:
@@ -36,7 +36,7 @@ VUpos Vcc VCM +5V
*Selected Circuit Analyses: *Selected Circuit Analyses:
.AC DEC 10 20 200k .AC DEC 10 20 200k
.CONTROL .CONTROL
SWEEP I_abc LIST 1uA 10uA 100uA SWEEP I_abc LIST 1uA 10uA 100uA 500uA
.ENDC .ENDC
*Models and Subcircuits: *Models and Subcircuits:

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