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Cleaned up Schematics

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Erik Tóth
2026-03-18 11:01:39 +01:00
parent f0c2168e2b
commit a24b15c27b
493 changed files with 3025728 additions and 3024156 deletions
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142
dev/analog/ETOTH-Log_Amp_Diode/Project Outputs for Log_Amp_Diode/Log_Amp_Diode.nsx
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@@ -1,72 +1,72 @@
Log_Amp_Diode
*SPICE Netlist generated by Advanced Sim server on 19.10.2025 11:32:26
.options MixedSimGenerated
*Schematic Netlist:
DD U_out NetD_C DI_1N4001
XIC1A 0 NetD_C VCC VEE U_out TL074
RR U_in NetD_C 5k
VU_mess U_out 0 0
VV_var U_in 0 -2
VVneg 0 VEE 15
VVpos VCC 0 15
.PLOT TRAN {i(U_mess)} =PLOT(1) =AXIS(1) =NAME(I_ABC) =UNITS(A)
*Selected Circuit Analyses:
.TRAN 0.1u 5u 0 0.1u
.CONTROL
SWEEP V_var LIST 0.25 0.5 1 2
.ENDC
*Models and Subcircuits:
***************************************************************************************************************************************
*SRC=1N4001;DI_1N4001;Diodes;Si; 50.0V 1.00A 3.00us Diodes, Inc. diode
.MODEL DI_1N4001 D ( IS=76.9p RS=42.0m BV=50.0 IBV=5.00u
+ CJO=39.8p M=0.333 N=1.45 TT=4.32u )
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
Log_Amp_Diode
*SPICE Netlist generated by Advanced Sim server on 19.10.2025 11:32:26
.options MixedSimGenerated
*Schematic Netlist:
DD U_out NetD_C DI_1N4001
XIC1A 0 NetD_C VCC VEE U_out TL074
RR U_in NetD_C 5k
VU_mess U_out 0 0
VV_var U_in 0 -2
VVneg 0 VEE 15
VVpos VCC 0 15
.PLOT TRAN {i(U_mess)} =PLOT(1) =AXIS(1) =NAME(I_ABC) =UNITS(A)
*Selected Circuit Analyses:
.TRAN 0.1u 5u 0 0.1u
.CONTROL
SWEEP V_var LIST 0.25 0.5 1 2
.ENDC
*Models and Subcircuits:
***************************************************************************************************************************************
*SRC=1N4001;DI_1N4001;Diodes;Si; 50.0V 1.00A 3.00us Diodes, Inc. diode
.MODEL DI_1N4001 D ( IS=76.9p RS=42.0m BV=50.0 IBV=5.00u
+ CJO=39.8p M=0.333 N=1.45 TT=4.32u )
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
.END

20
dev/analog/ETOTH-Log_Amp_Diode/Project Outputs for Log_Amp_Diode/Status Report.Txt
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@@ -1,10 +1,10 @@
Output: Mixed Sim
Type : AdvSimNetlist
From : Project [Log_Amp_Diode.PrjPcb]
Generated File[Log_Amp_Diode.nsx]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 12:34:57 On 07.07.2025
Output: Mixed Sim
Type : AdvSimNetlist
From : Project [Log_Amp_Diode.PrjPcb]
Generated File[Log_Amp_Diode.nsx]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 12:34:57 On 07.07.2025