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Cleaned up Schematics

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Erik Tóth
2026-03-18 11:01:39 +01:00
parent f0c2168e2b
commit a24b15c27b
493 changed files with 3025728 additions and 3024156 deletions
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2162
dev/analog/ETOTH-Log_Amp_Transistor/Log_Amp_Transistor.PrjPcb
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dev/analog/ETOTH-Log_Amp_Transistor/Log_Amp_Transistor.PrjPcbStructure
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Record=TopLevelDocument|FileName=Log_Amp_Transistor.SchDoc|SheetNumber=1
Record=TopLevelDocument|FileName=Log_Amp_Transistor.SchDoc|SheetNumber=1

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dev/analog/ETOTH-Log_Amp_Transistor/Project Outputs for Log_Amp_Transistor/Log_Amp_Transistor.nsx
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Log_Amp_Transistor
*SPICE Netlist generated by Advanced Sim server on 18.11.2025 13:26:39
.options MixedSimGenerated
*Schematic Netlist:
XIC1A 0 NetIC1_2 VCC VEE NetIC1_1 TL074
XIC1B 0 NetIC1_6 VCC VEE IN1 TL074
RR_1a NetR_1a_1 NetIC1_6 55.489k
RR_1b NetIC1_6 IN1 1k
RR_E NetIC1_1 NetR_E_2 8k
RR_ref NetIC1_2 VEE 500k
QT1a NetIC1_2 0 NetR_E_2 2N2907
QT1b OUT1 IN1 NetR_E_2 2N2907
VU_ctrl NetR_1a_1 0 1V
VU_mess OUT1 0 0
VVneg 0 VEE +5V
VVpos VCC 0 +5V
.PLOT DC {i(U_mess)} =PLOT(1) =AXIS(1) =NAME(I_out (PNP)) =UNITS(A) =RGB(0, 0, 255)
*Selected Circuit Analyses:
.DC U_ctrl -2 2 2.5m
*Models and Subcircuits:
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
*2N2907 MCE 5-27-97
*Ref: Motorola Small-Signal Device databook, Q4/94
*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
Log_Amp_Transistor
*SPICE Netlist generated by Advanced Sim server on 18.11.2025 13:26:39
.options MixedSimGenerated
*Schematic Netlist:
XIC1A 0 NetIC1_2 VCC VEE NetIC1_1 TL074
XIC1B 0 NetIC1_6 VCC VEE IN1 TL074
RR_1a NetR_1a_1 NetIC1_6 55.489k
RR_1b NetIC1_6 IN1 1k
RR_E NetIC1_1 NetR_E_2 8k
RR_ref NetIC1_2 VEE 500k
QT1a NetIC1_2 0 NetR_E_2 2N2907
QT1b OUT1 IN1 NetR_E_2 2N2907
VU_ctrl NetR_1a_1 0 1V
VU_mess OUT1 0 0
VVneg 0 VEE +5V
VVpos VCC 0 +5V
.PLOT DC {i(U_mess)} =PLOT(1) =AXIS(1) =NAME(I_out (PNP)) =UNITS(A) =RGB(0, 0, 255)
*Selected Circuit Analyses:
.DC U_ctrl -2 2 2.5m
*Models and Subcircuits:
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
*2N2907 MCE 5-27-97
*Ref: Motorola Small-Signal Device databook, Q4/94
*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
.END

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dev/analog/ETOTH-Log_Amp_Transistor/Project Outputs for Log_Amp_Transistor/Status Report.Txt
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Output: Mixed Sim
Type : AdvSimNetlist
From : Project [Log_Amp_Transistor.PrjPcb]
Generated File[Log_Amp_Transistor.nsx]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 17:29:55 On 11.11.2025
Output: Mixed Sim
Type : AdvSimNetlist
From : Project [Log_Amp_Transistor.PrjPcb]
Generated File[Log_Amp_Transistor.nsx]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 17:29:55 On 11.11.2025

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dev/analog/ETOTH-Log_Amp_Transistor/__Previews/Log_Amp_Transistor.SchDocPreview
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dev/analog/ETOTH-Log_Amp_Transistor/project_sim_config.simcfg
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