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Cleaned up Schematics

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This commit is contained in:
Erik Tóth
2026-03-18 11:01:39 +01:00
parent f0c2168e2b
commit a24b15c27b
493 changed files with 3025728 additions and 3024156 deletions
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2162
dev/analog/Offset_test2/Offset_test2.PrjPcb
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dev/analog/Offset_test2/Offset_test2.PrjPcbStructure
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Record=TopLevelDocument|FileName=Sheet1.SchDoc|SheetNumber=1
Record=TopLevelDocument|FileName=Sheet1.SchDoc|SheetNumber=1

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dev/analog/Offset_test2/Project Logs for Offset_test2/Sheet1 SCH ECO 08.12.2025 11-33-56.LOG
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Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=R_S? New Designator=R_S1
Change Component Designator: Old Designator=R_S? New Designator=R_S2
Change Component Designator: Old Designator=Rb? New Designator=Rb1
Change Component Designator: Old Designator=Rc? New Designator=Rc1
Change Component Designator: Old Designator=U_single? New Designator=U_single1
Change Component Designator: Old Designator=U_var? New Designator=U_var1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=R_S? New Designator=R_S1
Change Component Designator: Old Designator=R_S? New Designator=R_S2
Change Component Designator: Old Designator=Rb? New Designator=Rb1
Change Component Designator: Old Designator=Rc? New Designator=Rc1
Change Component Designator: Old Designator=U_single? New Designator=U_single1
Change Component Designator: Old Designator=U_var? New Designator=U_var1

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dev/analog/Offset_test2/Project Outputs for Offset_test2/Offset_test2.nsx
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Offset_test2
*SPICE Netlist generated by Advanced Sim server on 08.12.2025 19:05:32
.options MixedSimGenerated
*Schematic Netlist:
XIC1A R.VMID VCM VAP 0 VCM TL074
XIC1B VCM u_inv VAP 0 U_CV_off TL074
XIC1C VCM NetIC1_9 VAP 0 -U_CV_off TL074
RR_inv_a U_CV_off NetIC1_9 1K
RR_inv_b NetIC1_9 -U_CV_off 1K
RR_S1 R.VMID VAP 220k
RR_S2 0 R.VMID 220k
RRa VAP u_inv 1k
RRb1 NetRb1_1 u_inv 1K
RRc1 u_inv U_CV_off 1K
VU_single1 VAP 0 +10V
VU_var NetRb1_1 0 0
.PLOT TRAN {v(U_CV_off)} =PLOT(1) =AXIS(1)
.PLOT TRAN {v(Rb1)} =PLOT(2) =AXIS(1)
.PLOT TRAN {v(u_inv)} =PLOT(3) =AXIS(1)
.PLOT TRAN {v(Ra)} =PLOT(2) =AXIS(1) =UNITS(V)
.PLOT TRAN {v(-U_CV_off)} =PLOT(1) =AXIS(1)
*Selected Circuit Analyses:
.TRAN 0.1u 5u 0 0.1u
.CONTROL
SWEEP Ra LIST 833R 1k 1.25k
.ENDC
*Models and Subcircuits:
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
Offset_test2
*SPICE Netlist generated by Advanced Sim server on 08.12.2025 19:05:32
.options MixedSimGenerated
*Schematic Netlist:
XIC1A R.VMID VCM VAP 0 VCM TL074
XIC1B VCM u_inv VAP 0 U_CV_off TL074
XIC1C VCM NetIC1_9 VAP 0 -U_CV_off TL074
RR_inv_a U_CV_off NetIC1_9 1K
RR_inv_b NetIC1_9 -U_CV_off 1K
RR_S1 R.VMID VAP 220k
RR_S2 0 R.VMID 220k
RRa VAP u_inv 1k
RRb1 NetRb1_1 u_inv 1K
RRc1 u_inv U_CV_off 1K
VU_single1 VAP 0 +10V
VU_var NetRb1_1 0 0
.PLOT TRAN {v(U_CV_off)} =PLOT(1) =AXIS(1)
.PLOT TRAN {v(Rb1)} =PLOT(2) =AXIS(1)
.PLOT TRAN {v(u_inv)} =PLOT(3) =AXIS(1)
.PLOT TRAN {v(Ra)} =PLOT(2) =AXIS(1) =UNITS(V)
.PLOT TRAN {v(-U_CV_off)} =PLOT(1) =AXIS(1)
*Selected Circuit Analyses:
.TRAN 0.1u 5u 0 0.1u
.CONTROL
SWEEP Ra LIST 833R 1k 1.25k
.ENDC
*Models and Subcircuits:
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
.END

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dev/analog/Offset_test2/__Previews/Sheet1.$$$Preview
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dev/analog/Offset_test2/__Previews/Sheet1.SchDocPreview
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dev/analog/Offset_test2/project_sim_config.simcfg
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