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Cleaned up Schematics

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Erik Tóth
2026-03-18 11:01:39 +01:00
parent f0c2168e2b
commit a24b15c27b
493 changed files with 3025728 additions and 3024156 deletions
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34
dev/analog/VCF_LM13700_StateVariable/Project Logs for VCF_LM13700_StateVariable/VCF_LM13700_StateVariable SCH ECO 01.10.2025 19-22-58.LOG
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Change Component Designator: Old Designator=C? New Designator=C1
Change Component Designator: Old Designator=C? New Designator=C2
Change Component Designator: Old Designator=I? New Designator=I1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=R? New Designator=R1
Change Component Designator: Old Designator=R? New Designator=R2
Change Component Designator: Old Designator=R? New Designator=R3
Change Component Designator: Old Designator=R? New Designator=R4
Change Component Designator: Old Designator=R? New Designator=R5
Change Component Designator: Old Designator=R? New Designator=R6
Change Component Designator: Old Designator=R? New Designator=R7
Change Component Designator: Old Designator=R? New Designator=R8
Change Component Designator: Old Designator=R? New Designator=R9
Change Component Designator: Old Designator=C? New Designator=C1
Change Component Designator: Old Designator=C? New Designator=C2
Change Component Designator: Old Designator=I? New Designator=I1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=IC? New Designator=IC1
Change Component Designator: Old Designator=R? New Designator=R1
Change Component Designator: Old Designator=R? New Designator=R2
Change Component Designator: Old Designator=R? New Designator=R3
Change Component Designator: Old Designator=R? New Designator=R4
Change Component Designator: Old Designator=R? New Designator=R5
Change Component Designator: Old Designator=R? New Designator=R6
Change Component Designator: Old Designator=R? New Designator=R7
Change Component Designator: Old Designator=R? New Designator=R8
Change Component Designator: Old Designator=R? New Designator=R9

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dev/analog/VCF_LM13700_StateVariable/Project Logs for VCF_LM13700_StateVariable/VCF_LM13700_StateVariable SCH ECO 01.10.2025 19-25-53.LOG
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Change Component Designator: Old Designator=R? New Designator=R10
Change Component Designator: Old Designator=R? New Designator=R10

282
dev/analog/VCF_LM13700_StateVariable/Project Outputs for VCF_LM13700_StateVariable/VCF_LM13700_StateVariable.nsx
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VCF_LM13700_StateVariable
*SPICE Netlist generated by Advanced Sim server on 21.12.2025 11:31:08
.options MixedSimGenerated
*Schematic Netlist:
CC1 VCM NetC1_2 1nF
CC2 VCM NetC2_2 1nF
II_abc VCM NetI_abc_2 0
XIC1A NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
XIC1B NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
XIC1C NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
XIC1D NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
XIC1E NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
RR1 VCM NetIC1_3 1k
RR2 NetIC1_14 Uin 10k
RR3 BP_Out NetIC1_3 20k
RR4 VCM NetIC1_14 1K
RR5 0 LP_Out 5.1k
RR6 VCM NetIC1_13 1k
RR7 0 BP_Out 5.1k
RR8 BP_Out NetIC1_13 20k
RR9 LP_Out NetIC1_13 20k
RR10 VCM NetIC1_4 1k
VUe Uin VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
VUneg VCM 0 +5V
VUpos Vcc VCM +5V
.PLOT AC {dB(v(BP_Out))} =PLOT(1) =AXIS(1) =NAME(BP) =UNITS(dB)
.PLOT AC {dB(v(LP_Out))} =PLOT(2) =AXIS(1) =NAME(LP) =UNITS(dB)
*Selected Circuit Analyses:
.AC DEC 10 20 200k
.CONTROL
SWEEP I_abc LIST 1uA 10uA 100uA 500uA
.ENDC
*Models and Subcircuits:
* A dual opamp ngspice model
* file name: LM13700-DUAL.ckt
.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
+ 2out 2in- 2in+ 2Dbias 2ABin
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
* LM13700 Dual Operational Transconductance Amplifier
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
*
* Amplifier Bias Input
* | Diode Bias
* | | Positive Input
* | | | Negative Input
* | | | | Output
* | | | | | Negative power supply
* | | | | | | Buffer Input
* | | | | | | | Buffer Output
* | | | | | | | | Positive power supply
* | | | | | | | | |
.SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11
*
* Features:
* gm adjustable over 6 decades.
* Excellent gm linearity.
* Linearizing diodes.
* Wide supply range of +/-2V to +/-22V.
*
* Note: This model is single-pole in nature and over-estimates
* AC bandwidth and phase margin (stability) by over 2X.
* Although refinement may be possible in the future, please
* use benchtesting to finalize AC circuit design.
*
* Note: Model is for single device only and simulated
* supply current is 1/2 of total device current.
*
******************************************************
*
C1 6 4 4.8P
C2 3 6 4.8P
* Output capacitor
C3 5 6 6.26P
D1 2 4 DX
D2 2 3 DX
D3 11 21 DX
D4 21 22 DX
D5 1 26 DX
D6 26 27 DX
D7 5 29 DX
D8 28 5 DX
D10 31 25 DX
* Clamp for -CMR
D11 28 25 DX
* Ios source
F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9
F2 11 5 V2 1.022
F3 25 6 V3 1.0
F4 5 6 V1 1.022
* Output impedance
F5 5 0 POLY(2) V3 V7 0 0 0 0 1
G1 0 33 5 0 .55E-3
I1 11 6 300U
Q1 24 32 31 QX1
Q2 23 3 31 QX2
Q3 11 7 30 QZ
Q4 11 30 8 QY
V1 22 24 0V
V2 22 23 0V
V3 27 6 0V
V4 11 29 1.4
V5 28 6 1.2
V6 4 32 0V
V7 33 0 0V
.MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QY NPN (IS=6E-15 BF=50)
.MODEL QZ NPN (IS=5E-16 BF=266)
.MODEL DX D (IS=5E-16)
.ENDS
*$
XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
.ends
VCF_LM13700_StateVariable
*SPICE Netlist generated by Advanced Sim server on 21.12.2025 11:31:08
.options MixedSimGenerated
*Schematic Netlist:
CC1 VCM NetC1_2 1nF
CC2 VCM NetC2_2 1nF
II_abc VCM NetI_abc_2 0
XIC1A NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
XIC1B NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
XIC1C NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
XIC1D NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
XIC1E NetI_abc_2 NetIC1_15 NetIC1_14 NetIC1_13 NetC2_2 0 NetC2_2 BP_Out LP_Out
+ NetC1_2 Vcc NetC1_2 NetIC1_4 NetIC1_3 NetIC1_2 NetI_abc_2 LM13700-DUAL
RR1 VCM NetIC1_3 1k
RR2 NetIC1_14 Uin 10k
RR3 BP_Out NetIC1_3 20k
RR4 VCM NetIC1_14 1K
RR5 0 LP_Out 5.1k
RR6 VCM NetIC1_13 1k
RR7 0 BP_Out 5.1k
RR8 BP_Out NetIC1_13 20k
RR9 LP_Out NetIC1_13 20k
RR10 VCM NetIC1_4 1k
VUe Uin VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
VUneg VCM 0 +5V
VUpos Vcc VCM +5V
.PLOT AC {dB(v(BP_Out))} =PLOT(1) =AXIS(1) =NAME(BP) =UNITS(dB)
.PLOT AC {dB(v(LP_Out))} =PLOT(2) =AXIS(1) =NAME(LP) =UNITS(dB)
*Selected Circuit Analyses:
.AC DEC 10 20 200k
.CONTROL
SWEEP I_abc LIST 1uA 10uA 100uA 500uA
.ENDC
*Models and Subcircuits:
* A dual opamp ngspice model
* file name: LM13700-DUAL.ckt
.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
+ 2out 2in- 2in+ 2Dbias 2ABin
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
* LM13700 Dual Operational Transconductance Amplifier
* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
*
* Amplifier Bias Input
* | Diode Bias
* | | Positive Input
* | | | Negative Input
* | | | | Output
* | | | | | Negative power supply
* | | | | | | Buffer Input
* | | | | | | | Buffer Output
* | | | | | | | | Positive power supply
* | | | | | | | | |
.SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11
*
* Features:
* gm adjustable over 6 decades.
* Excellent gm linearity.
* Linearizing diodes.
* Wide supply range of +/-2V to +/-22V.
*
* Note: This model is single-pole in nature and over-estimates
* AC bandwidth and phase margin (stability) by over 2X.
* Although refinement may be possible in the future, please
* use benchtesting to finalize AC circuit design.
*
* Note: Model is for single device only and simulated
* supply current is 1/2 of total device current.
*
******************************************************
*
C1 6 4 4.8P
C2 3 6 4.8P
* Output capacitor
C3 5 6 6.26P
D1 2 4 DX
D2 2 3 DX
D3 11 21 DX
D4 21 22 DX
D5 1 26 DX
D6 26 27 DX
D7 5 29 DX
D8 28 5 DX
D10 31 25 DX
* Clamp for -CMR
D11 28 25 DX
* Ios source
F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9
F2 11 5 V2 1.022
F3 25 6 V3 1.0
F4 5 6 V1 1.022
* Output impedance
F5 5 0 POLY(2) V3 V7 0 0 0 0 1
G1 0 33 5 0 .55E-3
I1 11 6 300U
Q1 24 32 31 QX1
Q2 23 3 31 QX2
Q3 11 7 30 QZ
Q4 11 30 8 QY
V1 22 24 0V
V2 22 23 0V
V3 27 6 0V
V4 11 29 1.4
V5 28 6 1.2
V6 4 32 0V
V7 33 0 0V
.MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
.MODEL QY NPN (IS=6E-15 BF=50)
.MODEL QZ NPN (IS=5E-16 BF=266)
.MODEL DX D (IS=5E-16)
.ENDS
*$
XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
.ends
.END

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dev/analog/VCF_LM13700_StateVariable/VCF_LM13700_StateVariable.PrjPcb
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dev/analog/VCF_LM13700_StateVariable/VCF_LM13700_StateVariable.PrjPcbStructure
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Record=TopLevelDocument|FileName=VCF_LM13700_StateVariable.SchDoc|SheetNumber=1
Record=TopLevelDocument|FileName=VCF_LM13700_StateVariable.SchDoc|SheetNumber=1

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dev/analog/VCF_LM13700_StateVariable/__Previews/VCF_LM13700_StateVariable.SchDocPreview
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dev/analog/VCF_LM13700_StateVariable/project_sim_config.simcfg
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