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Cleaned up Schematics

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This commit is contained in:
Erik Tóth
2026-03-18 11:01:39 +01:00
parent f0c2168e2b
commit a24b15c27b
493 changed files with 3025728 additions and 3024156 deletions
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2162
dev/analog/VCO/OPV_Variante_E4U/OPV_Variante_E4U.PrjPcb
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dev/analog/VCO/OPV_Variante_E4U/OPV_Variante_E4U.PrjPcbStructure
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Record=TopLevelDocument|FileName=VCO.SchDoc|SheetNumber=1
Record=TopLevelDocument|FileName=VCO.SchDoc|SheetNumber=1

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dev/analog/VCO/OPV_Variante_E4U/__Previews/VCO.SchDocPreview
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dev/analog/VCO/OPV_Variante_E4U/project_sim_config.simcfg
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dev/analog/VCO/SAW_EXPL/Project Outputs for SAW_EXPL/SAW_EXPL.nsx
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SAW_EXPL
*SPICE Netlist generated by Advanced Sim server on 16.11.2025 16:38:57
.options MixedSimGenerated
*Schematic Netlist:
XIC1A 0 NetIC1_2 VAP GND Ue TL074
XIC1B NetIC1_5 NetIC1_6 VAP GND Ua TL074
XICSA R.VMID 0 VAP GND 0 LF411
XICSB R.VMID 0 VAP GND 0 LF411
RR1 NetR1_1 NetIC1_2 100k
RR2 NetIC1_2 Ue 50k
RR3a Ue NetIC1_5 10k
RR3b NetIC1_6 Ue 10k
RR4 Ua NetIC1_6 10k
RR5 GND NetR5_2 100k
RR6 NetR6_1 NetR5_2 33k
RR_S1 R.VMID VAP 220k
RR_S2 GND R.VMID 220k
RRoff NetIC1_2 GND 250k
JT 0 NetR5_2 NetIC1_5 BF256B
VU_single VAP GND +10V
VUin NetR1_1 0 DC 0 PULSE(-2 2 0 2.27m/2 2.27m/2 1u 2.27m 0) AC 1 0
VUsqr NetR6_1 0 DC 0 PULSE(-2 2 0 1u 1u 2.27m/2 2.27m) AC 1 0
.PLOT TRAN {v(Ue)} =PLOT(1) =AXIS(1) =NAME(U_TRI (angehoben)) =UNITS(V)
.PLOT TRAN {v(Ua)} =PLOT(2) =AXIS(1) =NAME(Ua) =UNITS(V)
.OPTIONS METHOD=GEAR MAXORD=2
*Selected Circuit Analyses:
.TRAN 45u 2.27m*3+15m 15m 45u
*Models and Subcircuits:
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
* ///////////////////////////////////////////////////////////////////
*//////////////////////////////////////////////////////////
*LF411 LOW OFFSET, LOW DRIFT JFET INPUT OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LF411 1 2 99 50 28
*
* PINOUT ORDER +IN -IN V+ V- OUT
*
*
*Features:
*Fast settling time (.01%) = 2uS
*High bandwidth = 3MHz
*High slew rate = 10V/uS
*Low offset voltage = .5mV
*Low supply current = 1.8mA
*
****************INPUT STAGE**************
*
IOS 2 1 25.0P
*^Input offset current
CI1 1 0 3P
CI2 2 0 3P
R1 1 3 1E12
R2 3 2 1E12
I1 99 4 1.0M
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 650
R4 6 50 650
*Fp2=28 MHZ
C4 5 6 4.372P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 800UA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 .8E-3 1
*Input offset voltage.^
R8 99 49 80K
R9 49 50 80K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.13
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.13
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 5 6 20E-3
R5 98 9 10MEG
VA3 9 11 0
*Fp1=18 HZ
C3 98 11 857.516P
*
***************POLE STAGE***************
*
*Fp=30 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 5.305E-15
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 144.7M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 99 50 VA7 1
F5 99 23 VA8 1
D5 21 23 DX
VA7 99 21 0
D6 23 99 DX
E1 99 26 99 15 1
VA8 26 27 0
R16 27 28 50
V5 28 25 0.646V
D4 25 15 DX
V4 24 28 0.646V
D3 15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12)
*
.ENDS
*PHILIPS SEMICONDUCTORS Version: 1.0
*Filename: bf256a_bf256b_philips
*
.MODEL BF256B NJF
+(
+ VTO = -2.3085E+000
+ BETA = 1.09045E-003
+ LAMBDA = 2.31754E-002
+ RD = 7.77648E+000
+ RS = 7.77648E+000
+ IS = 2.59121E-016
+ CGS = 2.00000E-012
+ CGD = 2.20000E-012
+ PB = 9.91494E-001
+ FC = 5.00000E-001
+)
SAW_EXPL
*SPICE Netlist generated by Advanced Sim server on 16.11.2025 16:38:57
.options MixedSimGenerated
*Schematic Netlist:
XIC1A 0 NetIC1_2 VAP GND Ue TL074
XIC1B NetIC1_5 NetIC1_6 VAP GND Ua TL074
XICSA R.VMID 0 VAP GND 0 LF411
XICSB R.VMID 0 VAP GND 0 LF411
RR1 NetR1_1 NetIC1_2 100k
RR2 NetIC1_2 Ue 50k
RR3a Ue NetIC1_5 10k
RR3b NetIC1_6 Ue 10k
RR4 Ua NetIC1_6 10k
RR5 GND NetR5_2 100k
RR6 NetR6_1 NetR5_2 33k
RR_S1 R.VMID VAP 220k
RR_S2 GND R.VMID 220k
RRoff NetIC1_2 GND 250k
JT 0 NetR5_2 NetIC1_5 BF256B
VU_single VAP GND +10V
VUin NetR1_1 0 DC 0 PULSE(-2 2 0 2.27m/2 2.27m/2 1u 2.27m 0) AC 1 0
VUsqr NetR6_1 0 DC 0 PULSE(-2 2 0 1u 1u 2.27m/2 2.27m) AC 1 0
.PLOT TRAN {v(Ue)} =PLOT(1) =AXIS(1) =NAME(U_TRI (angehoben)) =UNITS(V)
.PLOT TRAN {v(Ua)} =PLOT(2) =AXIS(1) =NAME(Ua) =UNITS(V)
.OPTIONS METHOD=GEAR MAXORD=2
*Selected Circuit Analyses:
.TRAN 45u 2.27m*3+15m 15m 45u
*Models and Subcircuits:
*TL074
*Quad LoNoise JFETInput OpAmp pkg:DIP14
*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | Positive Power Supply
* | | | Negative Power Supply
* | | | | Output
* | | | | |
.SUBCKT TL074 1 2 3 4 5
C1 11 12 3.498E-12
C2 6 7 15E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
BGND 99 0 V=V(3)*.5 + V(4)*.5
BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
+ I(VLP)*5E6 - I(VLN)*5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.2
VE 54 4 DC 2.2
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800E-18)
.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
.ENDS TL074
* ///////////////////////////////////////////////////////////////////
*//////////////////////////////////////////////////////////
*LF411 LOW OFFSET, LOW DRIFT JFET INPUT OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LF411 1 2 99 50 28
*
* PINOUT ORDER +IN -IN V+ V- OUT
*
*
*Features:
*Fast settling time (.01%) = 2uS
*High bandwidth = 3MHz
*High slew rate = 10V/uS
*Low offset voltage = .5mV
*Low supply current = 1.8mA
*
****************INPUT STAGE**************
*
IOS 2 1 25.0P
*^Input offset current
CI1 1 0 3P
CI2 2 0 3P
R1 1 3 1E12
R2 3 2 1E12
I1 99 4 1.0M
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 650
R4 6 50 650
*Fp2=28 MHZ
C4 5 6 4.372P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 800UA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 .8E-3 1
*Input offset voltage.^
R8 99 49 80K
R9 49 50 80K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.13
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.13
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 5 6 20E-3
R5 98 9 10MEG
VA3 9 11 0
*Fp1=18 HZ
C3 98 11 857.516P
*
***************POLE STAGE***************
*
*Fp=30 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 5.305E-15
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 144.7M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 99 50 VA7 1
F5 99 23 VA8 1
D5 21 23 DX
VA7 99 21 0
D6 23 99 DX
E1 99 26 99 15 1
VA8 26 27 0
R16 27 28 50
V5 28 25 0.646V
D4 25 15 DX
V4 24 28 0.646V
D3 15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12)
*
.ENDS
*PHILIPS SEMICONDUCTORS Version: 1.0
*Filename: bf256a_bf256b_philips
*
.MODEL BF256B NJF
+(
+ VTO = -2.3085E+000
+ BETA = 1.09045E-003
+ LAMBDA = 2.31754E-002
+ RD = 7.77648E+000
+ RS = 7.77648E+000
+ IS = 2.59121E-016
+ CGS = 2.00000E-012
+ CGD = 2.20000E-012
+ PB = 9.91494E-001
+ FC = 5.00000E-001
+)
.END

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dev/analog/VCO/SAW_EXPL/SAW_EXPL.PrjPcb
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dev/analog/VCO/SAW_EXPL/SAW_EXPL.PrjPcbStructure
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Record=TopLevelDocument|FileName=SAW_EXPL.SchDoc|SheetNumber=1
Record=TopLevelDocument|FileName=SAW_EXPL.SchDoc|SheetNumber=1

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dev/analog/VCO/SAW_EXPL/__Previews/SAW_EXPL.SchDocPreview
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dev/analog/VCO/SAW_EXPL/project_sim_config.simcfg
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dev/analog/VCO/VCO_OPV_Boehmer/VCO.PrjPcb
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dev/analog/VCO/VCO_OPV_Boehmer/VCO.PrjPcbStructure
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Record=TopLevelDocument|FileName=VCO_neu.SchDoc|SheetNumber=1
Record=TopLevelDocument|FileName=VCO_neu.SchDoc|SheetNumber=1

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dev/analog/VCO/VCO_OPV_Boehmer/__Previews/Integrator.SchDocPreview
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dev/analog/VCO/VCO_OPV_Boehmer/__Previews/VCO.SchDocPreview
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dev/analog/VCO/VCO_OPV_Boehmer/__Previews/VCO_neu.SchDocPreview
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dev/analog/VCO/VCO_OPV_Boehmer/project_sim_config.simcfg
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dev/analog/VCO/VCO_TRI_SQR/VCO_TRI_SQR.PrjPcb
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dev/analog/VCO/VCO_TRI_SQR/VCO_TRI_SQR.PrjPcbStructure
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Record=TopLevelDocument|FileName=VCO_TRI_SQR.SchDoc|SheetNumber=1
Record=TopLevelDocument|FileName=VCO_TRI_SQR.SchDoc|SheetNumber=1

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dev/analog/VCO/VCO_TRI_SQR/__Previews/VCO_TRI_SQR.SchDocPreview
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dev/analog/VCO/VCO_TRI_SQR/project_sim_config.simcfg
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