diff --git a/lab/VCF/Aufbau_Steckbrett.brd b/lab/VCF/Aufbau_Steckbrett.brd new file mode 100644 index 0000000..33d6a72 --- /dev/null +++ b/lab/VCF/Aufbau_Steckbrett.brd @@ -0,0 +1 @@ +Axial Resistor, 10.16 mm pitch, 8.50 mm body length, 2.50 mm body diameter <p>Axial Resistor package with 10.16 mm pitch (lead spacing), 0.63 mm lead diameter, 8.50 mm body length and 2.50 mm body diameter</p>>NAME>VALUE16-DIP, 2.54 mm (0.10 in) pitch, 7.62 mm (0.30 in) span, 19.69 X 6.6 X 5.08 mm body<p>16-pin DIP package with 2.54 mm (0.10 in) pitch, 7.62 mm (0.30 in) span with body size 19.69 X 6.6 X 5.08 mm</p>>NAME>VALUE>NAME>VALUEAxial Resistor, 10.16 mm pitch, 8.50 mm body length, 2.50 mm body diameter <p>Axial Resistor package with 10.16 mm pitch (lead spacing), 0.63 mm lead diameter, 8.50 mm body length and 2.50 mm body diameter</p>16-DIP, 2.54 mm (0.10 in) pitch, 7.62 mm (0.30 in) span, 19.69 X 6.6 X 5.08 mm body<p>16-pin DIP package with 2.54 mm (0.10 in) pitch, 7.62 mm (0.30 in) span with body size 19.69 X 6.6 X 5.08 mm</p><b>EAGLE Design Rules</b><p>Die Standard-Design-Rules sind so gewählt, dass sie für die meisten Anwendungen passen. Sollte ihre Platine besondere Anforderungen haben, treffen Sie die erforderlichenEinstellungen hier und speichern die Design Rules unter einem neuen Namen ab.<b>EAGLE Design Rules</b><p>The default Design Rules have been set to covera wide range of applications. Your particular designmay have different requirements, so please make thenecessary adjustments and save your customizeddesign rules under a new name.Since Version 8.3, EAGLE supports URNs for individual library assets (packages, symbols, and devices). The URNs of those assets will not be understood (or retained) with this version.Since Version 8.3, EAGLE supports the association of 3D packages with devices in libraries, schematics, and board files. Those 3D packages will not be understood (or retained) with this version.Since Version 8.4, EAGLE supports properties for SPICE simulation. Probes in schematics and SPICE mapping objects found in parts and library devices will not be understood with this version. Update EAGLE to the latest version for full support of SPICE simulation. \ No newline at end of file diff --git a/lab/VCF/Aufbau_Steckbrett.png b/lab/VCF/Aufbau_Steckbrett.png new file mode 100644 index 0000000..99200eb Binary files /dev/null and b/lab/VCF/Aufbau_Steckbrett.png differ diff --git a/lab/VCF/TEK0000.JPG b/lab/VCF/TEK0000.JPG new file mode 100644 index 0000000..09fb75a Binary files /dev/null and b/lab/VCF/TEK0000.JPG differ diff --git a/lab/VCF/TEK0001.JPG b/lab/VCF/TEK0001.JPG new file mode 100644 index 0000000..36cb750 Binary files /dev/null and b/lab/VCF/TEK0001.JPG differ diff --git a/lab/VCF/VCF.xlsx b/lab/VCF/VCF.xlsx new file mode 100644 index 0000000..3fefada Binary files /dev/null and b/lab/VCF/VCF.xlsx differ