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DAC Software Test

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- Korrekte Software: Nur noch kleiner offset max. -+5mV
This commit is contained in:
Erik Tóth
2025-10-13 20:43:59 +02:00
parent 9a06790ce3
commit aec4e43ba8
10 changed files with 40 additions and 15 deletions
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dev/pcb/DESIGN_RULE_JLCPCB/4layer-1oz-jlc7628-1.2mm.stackup Normal file
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dev/pcb/DESIGN_RULE_JLCPCB/4layer-1oz.RUL Normal file
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SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SilkToSilkClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SilkToSilkClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=LPWLVDIS|DEFINEDBYLOGICALDOCUMENT=FALSE|SILKTOSILKCLEARANCE=0mil<69>
SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=NetAntennae|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=NetAntennae|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=NCXUJVOQ|DEFINEDBYLOGICALDOCUMENT=FALSE|NETANTENNAETOLERANCE=0mil<69>
SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=AssemblyTestpoint|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=AssemblyTestpoint|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=QMHMVIFF|DEFINEDBYLOGICALDOCUMENT=FALSE|TESTPOINTUNDERCOMPONENT=TRUE|MINSIZE=40mil|MAXSIZE=100mil|PREFEREDSIZE=60mil|MINHOLESIZE=0mil|MAXHOLESIZE=40mil|PREFEREDHOLESIZE=32mil|TESTPOINTGRID=1mil|USEGRID=TRUE|GRIDTOLERANCE=0.01mil|ALLOWSIDETOP=TRUE|ALLOWSIDEBOTTOM=TRUE<55>
SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=AssemblyTestPointUsage|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=AssemblyTestPointUsage|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=KWLVDNGG|DEFINEDBYLOGICALDOCUMENT=FALSE<53>
SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=UnpouredPolygon|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=UnpouredPolygon|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=TAQTXOXB|DEFINEDBYLOGICALDOCUMENT=FALSE<53>
SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=BoardOutlineClearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=BoardOutlineClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=CDWUHYUL|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=7.874mil|GENERICCLEARANCE=7.874mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES= <20>

23
dev/pcb/DESIGN_RULE_JLCPCB/JLC04121H-7628_1-2mm.csv Normal file
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@@ -0,0 +1,23 @@
Board Layer Stack
Number;Name;Type;Manufacturer;Material;Process;Thickness (mm);Weight (oz);Dk;Df;Orientation;Copper Orientation;Description;Constructions;Resin (%);Frequency (GHz);GlassTransTemp (°C)
;Top Overlay;Overlay;;;;;;;;;;;;;;
;Top Solder;Solder Mask;;Solder Resist;;0.01;;3.8;;;;;;;;
1;Top Layer;Signal;Altium Designer;Copper;ED;0.035;1;;;Top;Above;Copper Foil;;;;
;Prepreg 1;Prepreg;Altium Designer;7628*1;;0.2104;;4.4;0.02;;;;7628;48;1;180
2;Layer 1;Signal;Altium Designer;Copper;ED;0.0152;0.5;;;Not allowed;Above;Copper Foil;;;;
;Core;Core;;Core;;0.6;;4.6;;;;;;;;
3;Layer 2;Signal;Altium Designer;Copper;ED;0.0152;0.5;;;Not allowed;Below;Copper Foil;;;;
;Prepreg 2;Prepreg;Altium Designer;7628*1;;0.2104;;4.4;0.02;;;;7628;48;1;180
4;Bottom Layer;Signal;Altium Designer;Copper;ED;0.035;1;;;Bottom;Below;Copper Foil;;;;
;Bottom Solder;Solder Mask;;Solder Resist;;0.01;;3.8;;;;;;;;
;Bottom Overlay;Overlay;;;;;;;;;;;;;;
No impedances
Via types
#;Name;Type;Layers;Stack
1;Thru 1:4;Thru;Top Layer-Bottom Layer;Board Layer Stack
No back drills
1 Board Layer Stack
2 Number;Name;Type;Manufacturer;Material;Process;Thickness (mm);Weight (oz);Dk;Df;Orientation;Copper Orientation;Description;Constructions;Resin (%);Frequency (GHz);GlassTransTemp (°C)
3 ;Top Overlay;Overlay;;;;;;;;;;;;;;
4 ;Top Solder;Solder Mask;;Solder Resist;;0.01;;3.8;;;;;;;;
5 1;Top Layer;Signal;Altium Designer;Copper;ED;0.035;1;;;Top;Above;Copper Foil;;;;
6 ;Prepreg 1;Prepreg;Altium Designer;7628*1;;0.2104;;4.4;0.02;;;;7628;48;1;180
7 2;Layer 1;Signal;Altium Designer;Copper;ED;0.0152;0.5;;;Not allowed;Above;Copper Foil;;;;
8 ;Core;Core;;Core;;0.6;;4.6;;;;;;;;
9 3;Layer 2;Signal;Altium Designer;Copper;ED;0.0152;0.5;;;Not allowed;Below;Copper Foil;;;;
10 ;Prepreg 2;Prepreg;Altium Designer;7628*1;;0.2104;;4.4;0.02;;;;7628;48;1;180
11 4;Bottom Layer;Signal;Altium Designer;Copper;ED;0.035;1;;;Bottom;Below;Copper Foil;;;;
12 ;Bottom Solder;Solder Mask;;Solder Resist;;0.01;;3.8;;;;;;;;
13 ;Bottom Overlay;Overlay;;;;;;;;;;;;;;
14 No impedances
15 Via types
16 #;Name;Type;Layers;Stack
17 1;Thru 1:4;Thru;Top Layer-Bottom Layer;Board Layer Stack
18 No back drills

2
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