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https://github.com/erik-toth/audio-synth.git
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vorbereitung labor + expl saw
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SAW_EXPL
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*SPICE Netlist generated by Advanced Sim server on 16.11.2025 16:38:57
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.options MixedSimGenerated
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*Schematic Netlist:
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XIC1A 0 NetIC1_2 VAP GND Ue TL074
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XIC1B NetIC1_5 NetIC1_6 VAP GND Ua TL074
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XICSA R.VMID 0 VAP GND 0 LF411
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XICSB R.VMID 0 VAP GND 0 LF411
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RR1 NetR1_1 NetIC1_2 100k
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RR2 NetIC1_2 Ue 50k
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RR3a Ue NetIC1_5 10k
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RR3b NetIC1_6 Ue 10k
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RR4 Ua NetIC1_6 10k
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RR5 GND NetR5_2 100k
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RR6 NetR6_1 NetR5_2 33k
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RR_S1 R.VMID VAP 220k
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RR_S2 GND R.VMID 220k
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RRoff NetIC1_2 GND 250k
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JT 0 NetR5_2 NetIC1_5 BF256B
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VU_single VAP GND +10V
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VUin NetR1_1 0 DC 0 PULSE(-2 2 0 2.27m/2 2.27m/2 1u 2.27m 0) AC 1 0
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VUsqr NetR6_1 0 DC 0 PULSE(-2 2 0 1u 1u 2.27m/2 2.27m) AC 1 0
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.PLOT TRAN {v(Ue)} =PLOT(1) =AXIS(1) =NAME(U_TRI (angehoben)) =UNITS(V)
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.PLOT TRAN {v(Ua)} =PLOT(2) =AXIS(1) =NAME(Ua) =UNITS(V)
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.OPTIONS METHOD=GEAR MAXORD=2
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*Selected Circuit Analyses:
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.TRAN 45u 2.27m*3+15m 15m 45u
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*Models and Subcircuits:
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*TL074
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*Quad LoNoise JFETInput OpAmp pkg:DIP14
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*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
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* Connections:
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* Non-Inverting Input
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* | Inverting Input
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* | | Positive Power Supply
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* | | | Negative Power Supply
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* | | | | Output
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* | | | | |
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.SUBCKT TL074 1 2 3 4 5
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C1 11 12 3.498E-12
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C2 6 7 15E-12
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DC 5 53 DX
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DE 54 5 DX
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DLP 90 91 DX
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DLN 92 90 DX
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DP 4 3 DX
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BGND 99 0 V=V(3)*.5 + V(4)*.5
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BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
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+ I(VLP)*5E6 - I(VLN)*5E6
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GA 6 0 11 12 282.8E-6
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GCM 0 6 10 99 8.942E-9
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ISS 3 10 DC 195E-6
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HLIM 90 0 VLIM 1K
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J1 11 2 10 JX
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J2 12 1 10 JX
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R2 6 9 100E3
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RD1 4 11 3.536E3
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RD2 4 12 3.536E3
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RO1 8 5 150
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RO2 7 99 150
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RP 3 4 2.143E3
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RSS 10 99 1.026E6
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VB 9 0 DC 0
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VC 3 53 DC 2.2
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VE 54 4 DC 2.2
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VLIM 7 8 DC 0
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VLP 91 0 DC 25
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VLN 0 92 DC 25
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.MODEL DX D(IS=800E-18)
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.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
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.ENDS TL074
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* ///////////////////////////////////////////////////////////////////
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*//////////////////////////////////////////////////////////
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*LF411 LOW OFFSET, LOW DRIFT JFET INPUT OP-AMP MACRO-MODEL
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*//////////////////////////////////////////////////////////
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*
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* connections: non-inverting input
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* | inverting input
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* | | positive power supply
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* | | | negative power supply
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* | | | | output
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* | | | | |
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* | | | | |
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.SUBCKT LF411 1 2 99 50 28
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*
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* PINOUT ORDER +IN -IN V+ V- OUT
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*
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*
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*Features:
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*Fast settling time (.01%) = 2uS
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*High bandwidth = 3MHz
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*High slew rate = 10V/uS
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*Low offset voltage = .5mV
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*Low supply current = 1.8mA
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*
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****************INPUT STAGE**************
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*
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IOS 2 1 25.0P
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*^Input offset current
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CI1 1 0 3P
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CI2 2 0 3P
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R1 1 3 1E12
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R2 3 2 1E12
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I1 99 4 1.0M
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J1 5 2 4 JX
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J2 6 7 4 JX
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R3 5 50 650
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R4 6 50 650
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*Fp2=28 MHZ
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C4 5 6 4.372P
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*
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***********COMMON MODE EFFECT***********
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*
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I2 99 50 800UA
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*^Quiescent supply current
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EOS 7 1 POLY(1) 16 49 .8E-3 1
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*Input offset voltage.^
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R8 99 49 80K
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R9 49 50 80K
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*
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*********OUTPUT VOLTAGE LIMITING********
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V2 99 8 2.13
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D1 9 8 DX
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D2 10 9 DX
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V3 10 50 2.13
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*
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**************SECOND STAGE**************
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*
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EH 99 98 99 49 1
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G1 98 9 5 6 20E-3
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R5 98 9 10MEG
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VA3 9 11 0
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*Fp1=18 HZ
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C3 98 11 857.516P
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*
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***************POLE STAGE***************
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*
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*Fp=30 MHz
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G3 98 15 9 49 1E-6
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R12 98 15 1MEG
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C5 98 15 5.305E-15
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*
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*********COMMON-MODE ZERO STAGE*********
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*
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G4 98 16 3 49 1E-8
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L2 98 17 144.7M
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R13 17 16 1K
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*
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**************OUTPUT STAGE**************
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*
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F6 99 50 VA7 1
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F5 99 23 VA8 1
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D5 21 23 DX
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VA7 99 21 0
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D6 23 99 DX
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E1 99 26 99 15 1
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VA8 26 27 0
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R16 27 28 50
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V5 28 25 0.646V
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D4 25 15 DX
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V4 24 28 0.646V
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D3 15 24 DX
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*
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***************MODELS USED**************
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*
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.MODEL DX D(IS=1E-15)
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.MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12)
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*
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.ENDS
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*PHILIPS SEMICONDUCTORS Version: 1.0
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*Filename: bf256a_bf256b_philips
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*
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.MODEL BF256B NJF
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+(
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+ VTO = -2.3085E+000
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+ BETA = 1.09045E-003
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+ LAMBDA = 2.31754E-002
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+ RD = 7.77648E+000
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+ RS = 7.77648E+000
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+ IS = 2.59121E-016
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+ CGS = 2.00000E-012
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+ CGD = 2.20000E-012
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+ PB = 9.91494E-001
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+ FC = 5.00000E-001
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+)
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.END
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