Labormessung

dev/analog/ETOTH-Log_Amp_Transistor/Project Outputs for Log_Amp_Transistor/Log_Amp_Transistor.nsx

@@ -1,5 +1,5 @@
 Log_Amp_Transistor
-*SPICE Netlist generated by Advanced Sim server on 11.11.2025 17:52:27
+*SPICE Netlist generated by Advanced Sim server on 18.11.2025 13:26:39
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -19,7 +19,7 @@ VVpos VCC 0 +5V
 .PLOT DC {i(U_mess)} =PLOT(1) =AXIS(1) =NAME(I_out (PNP)) =UNITS(A) =RGB(0, 0, 255)
 
 *Selected Circuit Analyses:
-.DC U_ctrl -5 5 25m
+.DC U_ctrl -2 2 2.5m
 
 *Models and Subcircuits:
 *TL074

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/TRI-SQR-VCO_OTA_SS.nsx

@@ -1,5 +1,5 @@
 TRI-SQR-VCO_OTA_SS
-*SPICE Netlist generated by Advanced Sim server on 16.11.2025 16:24:16
+*SPICE Netlist generated by Advanced Sim server on 18.11.2025 14:07:43
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -55,6 +55,7 @@ VU_var NetR_CV_1 0 1
 .PLOT TRAN {v(U_TRI)} =PLOT(2) =AXIS(1) =NAME(U_TRI) =UNITS(V)
 .PLOT TRAN {v(U_SAW)} =PLOT(3) =AXIS(1) =NAME(U_SAW) =UNITS(V)
 .PLOT TRAN {v(U_PWM)} =PLOT(4) =AXIS(1) =NAME(U_PWM) =UNITS(V)
+.PLOT TRAN {i(U_mess)} =PLOT(5) =AXIS(1) =NAME(I_GND) =UNITS(A)
 .PLOT TRAN {v(U_in)} =PLOT(2) =AXIS(1) =NAME(U_in) =UNITS(V)
 
 .OPTIONS ABSTOL=1e-10 RELTOL=1e-2 VNTOL=1e-4 METHOD=GEAR MAXORD=2