Labormessung

2025-12-06 09:20:02 +00:00 · 2025-11-19 08:53:06 +01:00
parent 0702a4192b
commit b7d26b995e
148 changed files with 2960 additions and 3300 deletions
--- a/dev/analog/ETOTH-Log_Amp_Transistor/History/Log_Amp_Transistor.~(13).PrjPcb.Zip
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/History/Log_Amp_Transistor.~(13).PrjPcb.Zip
--- a/dev/analog/ETOTH-Log_Amp_Transistor/History/Log_Amp_Transistor.~(13).SchDoc.Zip
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/History/Log_Amp_Transistor.~(13).SchDoc.Zip
--- a/dev/analog/ETOTH-Log_Amp_Transistor/History/Log_Amp_Transistor.~(30).PrjPcb.Zip
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/History/Log_Amp_Transistor.~(30).PrjPcb.Zip
--- a/dev/analog/ETOTH-Log_Amp_Transistor/History/Log_Amp_Transistor.~(33).SchDoc.Zip
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/History/Log_Amp_Transistor.~(33).SchDoc.Zip
--- a/dev/analog/ETOTH-Log_Amp_Transistor/History/Simulation/Log_Amp_Transistor.~(16).sdf.Zip
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/History/Simulation/Log_Amp_Transistor.~(16).sdf.Zip
--- a/dev/analog/ETOTH-Log_Amp_Transistor/History/Simulation/Log_Amp_Transistor.~(31).sdf.Zip
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/History/Simulation/Log_Amp_Transistor.~(31).sdf.Zip
--- a/dev/analog/ETOTH-Log_Amp_Transistor/History/project_sim_config.~(13).simcfg.Zip
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/History/project_sim_config.~(13).simcfg.Zip
--- a/dev/analog/ETOTH-Log_Amp_Transistor/History/project_sim_config.~(28).simcfg.Zip
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/History/project_sim_config.~(28).simcfg.Zip
--- a/dev/analog/ETOTH-Log_Amp_Transistor/Log_Amp_Transistor.PrjPcb
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/Log_Amp_Transistor.PrjPcb
--- a/dev/analog/ETOTH-Log_Amp_Transistor/Log_Amp_Transistor.SchDoc
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/Log_Amp_Transistor.SchDoc
--- a/dev/analog/ETOTH-Log_Amp_Transistor/Project
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/Project
@@ -1,5 +1,5 @@
 Log_Amp_Transistor
-*SPICE Netlist generated by Advanced Sim server on 11.11.2025 17:52:27
+*SPICE Netlist generated by Advanced Sim server on 18.11.2025 13:26:39
 .options MixedSimGenerated

 *Schematic Netlist:
@@ -19,7 +19,7 @@ VVpos VCC 0 +5V
 .PLOT DC {i(U_mess)} =PLOT(1) =AXIS(1) =NAME(I_out (PNP)) =UNITS(A) =RGB(0, 0, 255)

 *Selected Circuit Analyses:
-.DC U_ctrl -5 5 25m
+.DC U_ctrl -2 2 2.5m

 *Models and Subcircuits:
 *TL074
--- a/dev/analog/ETOTH-Log_Amp_Transistor/Simulation/Log_Amp_Transistor.sdf
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/Simulation/Log_Amp_Transistor.sdf
--- a/dev/analog/ETOTH-Log_Amp_Transistor/__Previews/Log_Amp_Transistor.SchDocPreview
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/__Previews/Log_Amp_Transistor.SchDocPreview
--- a/dev/analog/ETOTH-Log_Amp_Transistor/project_sim_config.simcfg
+++ b/dev/analog/ETOTH-Log_Amp_Transistor/project_sim_config.simcfg