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PCB WIP 2

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All routing done, ready for review regarding the schematics, still have to do some silk screens...
This commit is contained in:
Erik Tóth
2025-12-27 01:02:47 +01:00
parent 3ec229c965
commit c661422a10
192 changed files with 54752 additions and 54 deletions
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753
dev/general/MainSys/MainSys.PrjPcb
View File

@@ -304,6 +304,124 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=TVEIXTYM
[Document16]
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AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=0
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DocumentUniqueId=
[Document17]
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AnnotateSuffix=
AnnotateScope=All
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DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=0
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
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DocumentPath=Project Outputs for MainSys\Design Rule Check - MAIN.html
DItemRevisionGUID=
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DocumentPath=Project Outputs for MainSys\MAIN-SlotHoles.TXT
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DocumentPath=Project Outputs for MainSys\MAIN.DRR
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DocumentPath=Project Outputs for MainSys\MAIN.EXTREP
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DocumentPath=Project Outputs for MainSys\MAIN.LDP
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[GeneratedDocument10]
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DItemRevisionGUID=
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DItemRevisionGUID=
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DocumentPath=Project Outputs for MainSys\MAIN_Paste_Top.gbr
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@@ -565,22 +687,22 @@ Name=Fabrication Outputs
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