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PCB WIP 2

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All routing done, ready for review regarding the schematics, still have to do some silk screens...
This commit is contained in:
Erik Tóth
2025-12-27 01:02:47 +01:00
parent 3ec229c965
commit c661422a10
192 changed files with 54752 additions and 54 deletions
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6
dev/general/MainSys/Project Logs for MainSys/MAIN PCB ECO 26.12.2025 22-48-50.LOG Normal file
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Add Pin To Net: Unknown Pin: Pin D1-1
Add Pin To Net: Unknown Pin: Pin D1-2
Add Pin To Net: Unknown Pin: Pin D2-1
Add Pin To Net: Unknown Pin: Pin D2-2
Add Class Member: Failed to add class member : Component D1 RCLAMP0521P-N
Add Class Member: Failed to add class member : Component D2 RCLAMP0521P-N