PCB WIP 2

All routing done, ready for review regarding the schematics, still have to do some silk screens...
This commit is contained in:
2025-12-27 01:02:47 +01:00
parent 3ec229c965
commit c661422a10
192 changed files with 54752 additions and 54 deletions

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Replace Part D1 D RCLAMP0521P-N in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\TOP.SchDoc with D RCLAMP0521P-N from DA_LIB.IntLib
Replace Part D2 D RCLAMP0521P-N in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\TOP.SchDoc with D RCLAMP0521P-N from DA_LIB.IntLib
Replace Part J1 J KH-TYPE-C-16P in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\TOP.SchDoc with J KH-TYPE-C-16P from DA_LIB.IntLib
Replace Part TP1 TP TESTPOINT in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\TOP.SchDoc with TP TESTPOINT from DA_LIB.IntLib
Replace Part TP2 TP TESTPOINT in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\TOP.SchDoc with TP TESTPOINT from DA_LIB.IntLib
Replace Part TP3 TP TESTPOINT in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\TOP.SchDoc with TP TESTPOINT from DA_LIB.IntLib
Replace Part TP4 TP TESTPOINT in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\TOP.SchDoc with TP TESTPOINT from DA_LIB.IntLib