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PCB WIP 2

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All routing done, ready for review regarding the schematics, still have to do some silk screens...
This commit is contained in:
Erik Tóth
2025-12-27 01:02:47 +01:00
parent 3ec229c965
commit c661422a10
192 changed files with 54752 additions and 54 deletions
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dev/general/MainSys/Project Outputs for MainSys/MAIN.LDP Normal file
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Layer Pairs Export File for PCB: C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\MAIN.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=main-roundholes.txt|DrillLayers=gtl,g1,g2,gbl
LayersSetName=Top_Bot_Slot_Holes|DrillFile=main-slotholes.txt|DrillLayers=gtl,g1,g2,gbl