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PCB WIP 2

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All routing done, ready for review regarding the schematics, still have to do some silk screens...
This commit is contained in:
Erik Tóth
2025-12-27 01:02:47 +01:00
parent 3ec229c965
commit c661422a10
192 changed files with 54752 additions and 54 deletions
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10
dev/general/MainSys/Project Outputs for MainSys/Status Report.Txt Normal file
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Output: Generates pick and place files
Type : Pick Place
From : Variant [[No Variations]] of Project [MainSys.PrjPcb]
Generated File[Pick Place for MAIN.csv]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 22:18:28 On 26.12.2025