Hilfe

dev/analog/ETOTH-TRI-SQR-VCO_OTA/Project Outputs for TRI-SQR-VCO_OTA/TRI-SQR-VCO_OTA.nsx

@@ -1,5 +1,9 @@
 TRI-SQR-VCO_OTA
+<<<<<<< HEAD
 *SPICE Netlist generated by Advanced Sim server on 08.10.2025 22:16:50
+=======
+*SPICE Netlist generated by Advanced Sim server on 08.10.2025 17:40:24
+>>>>>>> 715373b81cbca2add5bdb520f12f5bbd4d567628
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -44,16 +48,23 @@ RRoff NetIC3_2 Vee 650k
 QT1 NetC_an_1 0 NetC_an_2 2N2907
 QT2 NetT2_3 U_C NetC_an_2 2N2907
 JT_SAW 0 NetR_SAW_e_2 NetIC2_12 BF545B
+VU_I-GND-MESS NetU_I-GND-MESS_1 0 0
 VU_mess NetT2_3 NetIC1_16 0
 VU_messref NetR_E_2 NetIC2_7 0
+<<<<<<< HEAD
 VU_neg 0 Vee +9V
 VU_pos Vcc 0 +9V
+=======
+VU_neg NetU_I-GND-MESS_1 Vee 15
+VU_pos Vcc NetU_I-GND-MESS_1 15
+>>>>>>> 715373b81cbca2add5bdb520f12f5bbd4d567628
 VU_var NetR_CV_1 0 1
 
 .PLOT TRAN {v(U_SQR)} =PLOT(2) =AXIS(1) =NAME(U_SQR) =UNITS(V)
 .PLOT TRAN {v(U_TRI)} =PLOT(1) =AXIS(1) =NAME(U_TRI) =UNITS(V)
 .PLOT TRAN {v(U_SAW)} =PLOT(3) =AXIS(1) =NAME(U_SAW) =UNITS(V)
 .PLOT TRAN {v(U_PWM)} =PLOT(4) =AXIS(1) =NAME(PWM) =UNITS(V)
+.PLOT TRAN {i(U_I-GND-MESS)} =PLOT(5) =AXIS(1) =NAME(I_GND) =UNITS(A)
 
 .OPTIONS ITL4=100 METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:

dev/da_altium_lib/DA_LIB/TL047_QUAD.ckt

@@ -0,0 +1,80 @@
+* ===========================================================
+* TL074 QUAD OPERATIONAL AMPLIFIER MACROMODEL (Standalone)
+* Fully self-contained SPICE subcircuit, no external includes
+* Based on TI TL074 macromodel (Rev. 1989)
+* ===========================================================
+* Pin assignment (DIP-14):
+*  1:  OUT1
+*  2:  IN1-
+*  3:  IN1+
+*  4:  VCC+
+*  5:  IN2+
+*  6:  IN2-
+*  7:  OUT2
+*  8:  OUT3
+*  9:  IN3-
+* 10:  IN3+
+* 11:  VCC-
+* 12:  IN4+
+* 13:  IN4-
+* 14:  OUT4
+* ===========================================================
+
+.subckt TL074_QUAD  OUT1 IN1- IN1+  VCC+  IN2+ IN2- OUT2  OUT3 IN3- IN3+  VCC-  IN4+ IN4- OUT4
+
+* ========== OPAMP #1 ==========
+XU1 IN1+ IN1- VCC+ VCC- OUT1 TL074_CORE
+
+* ========== OPAMP #2 ==========
+XU2 IN2+ IN2- VCC+ VCC- OUT2 TL074_CORE
+
+* ========== OPAMP #3 ==========
+XU3 IN3+ IN3- VCC+ VCC- OUT3 TL074_CORE
+
+* ========== OPAMP #4 ==========
+XU4 IN4+ IN4- VCC+ VCC- OUT4 TL074_CORE
+
+.ends TL074_QUAD
+
+* ===========================================================
+* SINGLE TL074 OPAMP CORE MODEL (from TI 1989 macromodel)
+* ===========================================================
+.subckt TL074_CORE 1 2 3 4 5
+* 1: non-inv input
+* 2: inv input
+* 3: VCC+
+* 4: VCC-
+* 5: output
+
+  C1   11 12 3.498E-12
+  C2    6  7 15.00E-12
+  DC    5 53 DX
+  DE   54  5 DX
+  DLP  90 91 DX
+  DLN  92 90 DX
+  DP    4  3 DX
+  EGND 99  0 POLY(2) (3,0) (4,0) 0 .5 .5
+  FB    7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
+  GA    6  0 11 12 282.8E-6
+  GCM   0  6 10 99 8.942E-9
+  ISS   3 10 DC 195.0E-6
+  HLIM 90  0 VLIM 1K
+  J1   11  2 10 JX
+  J2   12  1 10 JX
+  R2    6  9 100.0E3
+  RD1   4 11 3.536E3
+  RD2   4 12 3.536E3
+  RO1   8  5 150
+  RO2   7 99 150
+  RP    3  4 2.143E3
+  RSS  10 99 1.026E6
+  VB    9  0 DC 0
+  VC    3 53 DC 2.200
+  VE   54  4 DC 2.200
+  VLIM  7  8 DC 0
+  VLP  91  0 DC 25
+  VLN   0 92 DC 25
+.MODEL DX D(IS=800.0E-18)
+.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
+.ends TL074_CORE
+

dev/digital/DAC_MCP4728/DAC_MCP4728.PrjPcbStructure

@@ -0,0 +1 @@
+Record=TopLevelDocument|FileName=DAC_MCP4728.SchDoc|SheetNumber=1

dev/digital/DAC_MCP4728_Test/.gitignore

@@ -0,0 +1,5 @@
+.pio
+.vscode/.browse.c_cpp.db*
+.vscode/c_cpp_properties.json
+.vscode/launch.json
+.vscode/ipch

dev/digital/DAC_MCP4728_Test/.vscode/extensions.json

@@ -0,0 +1,10 @@
+{
+    // See http://go.microsoft.com/fwlink/?LinkId=827846
+    // for the documentation about the extensions.json format
+    "recommendations": [
+        "platformio.platformio-ide"
+    ],
+    "unwantedRecommendations": [
+        "ms-vscode.cpptools-extension-pack"
+    ]
+}

dev/digital/DAC_MCP4728_Test/include/README

@@ -0,0 +1,37 @@
+
+This directory is intended for project header files.
+
+A header file is a file containing C declarations and macro definitions
+to be shared between several project source files. You request the use of a
+header file in your project source file (C, C++, etc) located in `src` folder
+by including it, with the C preprocessing directive `#include'.
+
+```src/main.c
+
+#include "header.h"
+
+int main (void)
+{
+ ...
+}
+```
+
+Including a header file produces the same results as copying the header file
+into each source file that needs it. Such copying would be time-consuming
+and error-prone. With a header file, the related declarations appear
+in only one place. If they need to be changed, they can be changed in one
+place, and programs that include the header file will automatically use the
+new version when next recompiled. The header file eliminates the labor of
+finding and changing all the copies as well as the risk that a failure to
+find one copy will result in inconsistencies within a program.
+
+In C, the convention is to give header files names that end with `.h'.
+
+Read more about using header files in official GCC documentation:
+
+* Include Syntax
+* Include Operation
+* Once-Only Headers
+* Computed Includes
+
+https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html

dev/digital/DAC_MCP4728_Test/lib/README

@@ -0,0 +1,46 @@
+
+This directory is intended for project specific (private) libraries.
+PlatformIO will compile them to static libraries and link into the executable file.
+
+The source code of each library should be placed in a separate directory
+("lib/your_library_name/[Code]").
+
+For example, see the structure of the following example libraries `Foo` and `Bar`:
+
+|--lib
+|  |
+|  |--Bar
+|  |  |--docs
+|  |  |--examples
+|  |  |--src
+|  |     |- Bar.c
+|  |     |- Bar.h
+|  |  |- library.json (optional. for custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html
+|  |
+|  |--Foo
+|  |  |- Foo.c
+|  |  |- Foo.h
+|  |
+|  |- README --> THIS FILE
+|
+|- platformio.ini
+|--src
+   |- main.c
+
+Example contents of `src/main.c` using Foo and Bar:
+```
+#include <Foo.h>
+#include <Bar.h>
+
+int main (void)
+{
+  ...
+}
+
+```
+
+The PlatformIO Library Dependency Finder will find automatically dependent
+libraries by scanning project source files.
+
+More information about PlatformIO Library Dependency Finder
+- https://docs.platformio.org/page/librarymanager/ldf.html

dev/digital/DAC_MCP4728_Test/platformio.ini

@@ -0,0 +1,16 @@
+; PlatformIO Project Configuration File
+;
+;   Build options: build flags, source filter
+;   Upload options: custom upload port, speed and extra flags
+;   Library options: dependencies, extra library storages
+;   Advanced options: extra scripting
+;
+; Please visit documentation for the other options and examples
+; https://docs.platformio.org/page/projectconf.html
+
+[env:esp32-s3-devkitm-1]
+platform = espressif32
+board = esp32-s3-devkitm-1
+framework = arduino
+build_flags = -DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT=1 -DARDUINO_USB_JTAG_ON_BOOT=1
+lib_deps = adafruit/Adafruit MCP4728@^1.0.10

dev/digital/DAC_MCP4728_Test/src/main.cpp

@@ -0,0 +1,82 @@
+#include <Wire.h>
+#include <Adafruit_MCP4728.h>
+
+#define BAUDRATE  115200
+
+#define I2C_SDA   15
+#define I2C_SCL   16
+#define I2C_FREQ  400000
+
+#define DAC_MAX   4095
+#define DAC_MIN   0
+#define VREF_mV   2048
+
+#define VREF_CONF_IN_USE MCP4728_VREF_INTERNAL
+
+#define PIN_BTN   40
+
+Adafruit_MCP4728 mcp;
+
+static uint16_t value_mV = VREF_mV;
+
+bool button_state_old = false;
+bool button_state_now = false;
+
+uint16_t voltage(uint16_t mV)
+{
+  return map(mV, 0, VREF_mV, DAC_MIN, DAC_MAX);
+}
+
+void setup() 
+{
+  Serial.begin(BAUDRATE);
+  delay(1000);
+  Serial.print("\n\rMCP4728 DAC Test");
+
+  Wire.begin(I2C_SDA, I2C_SCL);
+  Wire.setClock(I2C_FREQ);
+
+  pinMode(PIN_BTN, INPUT);
+
+  Serial.print("\n\rInitialisiere MCP4728...");
+  uint8_t attempts = 0;
+  while (!mcp.begin()) 
+  {
+    if(attempts > 20)
+    {
+      Serial.print("\n\rError: Es konnte nach 20 Versuchen kein IC gefunden werden. Überprüfe die Verkabelung und starte den ESP neu!");
+      for(;;);
+    }
+    Serial.print(".");
+    delay(100);
+    attempts++;
+  }
+  Serial.print("\n\rErfolgreich verbunden!");
+
+  mcp.setChannelValue(MCP4728_CHANNEL_A, 4095, VREF_CONF_IN_USE);
+  Serial.print("\n\rDAC-Kanal A auf 0 gesetzt");
+  delay(1000);
+}
+
+
+void loop() 
+{
+  button_state_now = digitalRead(PIN_BTN);
+  if (button_state_now != button_state_old) 
+  {
+    delay(10); // debounce delay
+    button_state_now = digitalRead(PIN_BTN);
+    if (button_state_now != button_state_old) 
+    {
+      button_state_old = button_state_now;
+      if (button_state_now == HIGH) 
+      {
+        if(value_mV < 2000) value_mV += (1000/12);
+        if(value_mV >= 2000) value_mV = 0;
+
+        if (mcp.setChannelValue(MCP4728_CHANNEL_A, voltage(value_mV), VREF_CONF_IN_USE)) Serial.printf("DAC A = %u -> mV: %u\r\n", voltage(value_mV), value_mV);
+        else Serial.println("Error: Neuer MCP4728 Wert konnte nicht gesetzt werden!");
+      }
+    }
+  }
+}

dev/digital/DAC_MCP4728_Test/test/README

@@ -0,0 +1,11 @@
+
+This directory is intended for PlatformIO Test Runner and project tests.
+
+Unit Testing is a software testing method by which individual units of
+source code, sets of one or more MCU program modules together with associated
+control data, usage procedures, and operating procedures, are tested to
+determine whether they are fit for use. Unit testing finds problems early
+in the development cycle.
+
+More information about PlatformIO Unit Testing:
+- https://docs.platformio.org/en/latest/advanced/unit-testing/index.html

dev/digital/ESP32-S3/ESP32-S3.PrjPcbStructure

@@ -0,0 +1 @@
+Record=TopLevelDocument|FileName=ESP32-S3.SchDoc|SheetNumber=1

dev/digital/ESP32-S3/Project Logs for ESP32-S3/ESP32-S3 SCH ECO 07.10.2025 08-42-44.LOG

@@ -0,0 +1 @@
+Replace Part IC? IC ESP32-S3R8 in C:\HTL\5AHEL\DA\github\audio-synth\dev\digital\ESP32-S3\ESP32-S3.SchDoc with IC ESP32-S3R8 from DA_LIB.IntLib

dev/digital/ESP32-S3/Project Logs for ESP32-S3/ESP32-S3 SCH ECO 07.10.2025 10-22-47.LOG

@@ -0,0 +1 @@
+Replace Part IC? IC ESP32-S3R8 in C:\HTL\5AHEL\DA\github\audio-synth\dev\digital\ESP32-S3\ESP32-S3.SchDoc with IC ESP32-S3R8 from DA_LIB.IntLib

dev/digital/ESP32-S3/Project Logs for ESP32-S3/ESP32-S3 SCH ECO 29.09.2025 17-41-18.LOG

@@ -0,0 +1 @@
+Replace Part IC? IC W25Q128JVSIQ in C:\HTL\5AHEL\DA\github\audio-synth\dev\digital\ESP32-S3\ESP32-S3.SchDoc with IC W25Q128JVSIQ from DA_LIB.IntLib

dev/digital/ESP32-S3/Project Logs for ESP32-S3/ESP32-S3 SCH ECO 29.09.2025 17-44-37.LOG

@@ -0,0 +1 @@
+Replace Part Y? Y X322540MPB4SI in C:\HTL\5AHEL\DA\github\audio-synth\dev\digital\ESP32-S3\ESP32-S3.SchDoc with Y X322540MPB4SI from DA_LIB.IntLib

dev/pcb/DESIGN_RULE_JLCPCB/4layer-1oz.RUL

@@ -0,0 +1,38 @@
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Clearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Clearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=SXABEUHD|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=4mil|GENERICCLEARANCE=4mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES=ClearanceObj_Arc-ClearanceObj_Via:50000;ClearanceObj_Arc-ClearanceObj_Hole:98425;ClearanceObj_Track-ClearanceObj_Via:50000;ClearanceObj_Track-ClearanceObj_Hole:98425;ClearanceObj_SMDPad-ClearanceObj_Via:50000;ClearanceObj_SMDPad-ClearanceObj_Hole:98425;ClearanceObj_THPad-ClearanceObj_Via:50000;ClearanceObj_THPad-ClearanceObj_Hole:98425;ClearanceObj_Via-ClearanceObj_Via:50000;ClearanceObj_Via-ClearanceObj_Fill:50000;ClearanceObj_Via-ClearanceObj_Poly:50000;ClearanceObj_Via-ClearanceObj_Region:50000;ClearanceObj_Via-ClearanceObj_Text:50000;ClearanceObj_Via-ClearanceObj_Hole:98425;ClearanceObj_Fill-ClearanceObj_Hole:98425;ClearanceObj_Poly-ClearanceObj_Hole:98425;ClearanceObj_Region-ClearanceObj_Hole:98425;ClearanceObj_Text-ClearanceObj_Hole:98425<32>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Width|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Width|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=FAIRCJNH|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=71497.9375mil|MINLIMIT=4mil|PREFEREDWIDTH=4mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=InPadClass('PowerPads')|SCOPE2EXPRESSION=All|NAME=PlaneConnectPowerPads|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=PIHAOJKT|DEFINEDBYLOGICALDOCUMENT=FALSE|PLANECONNECTSTYLE=Direct|RELIEFEXPANSION=20mil|RELIEFENTRIES=4|RELIEFCONDUCTORWIDTH=10mil|RELIEFAIRGAP=10mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PlaneConnect|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=KDFBURJC|DEFINEDBYLOGICALDOCUMENT=FALSE|PAD.PLANECONNECTSTYLE=Relief|PAD.RELIEFEXPANSION=11.811mil|PAD.RELIEFENTRIES=4|PAD.RELIEFCONDUCTORWIDTH=4mil|PAD.RELIEFAIRGAP=4mil|VIA.PLANECONNECTSTYLE=Direct|VIA.RELIEFEXPANSION=11.811mil|VIA.RELIEFENTRIES=4|VIA.RELIEFCONDUCTORWIDTH=5mil|VIA.RELIEFAIRGAP=5mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingTopology|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingTopology|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=JBODXEDS|DEFINEDBYLOGICALDOCUMENT=FALSE|TOPOLOGY=Shortest<73>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingPriority|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingPriority|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=FABPNCNQ|DEFINEDBYLOGICALDOCUMENT=FALSE|ROUTINGPRIORITY=0<>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingLayers|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingLayers|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=HBJKJJIF|DEFINEDBYLOGICALDOCUMENT=FALSE|TOP LAYER_V5=TRUE|MID LAYER 1_V5=TRUE|MID LAYER 2_V5=TRUE|MID LAYER 3_V5=TRUE|MID LAYER 4_V5=TRUE|MID LAYER 5_V5=TRUE|MID LAYER 6_V5=TRUE|MID LAYER 7_V5=TRUE|MID LAYER 8_V5=TRUE|MID LAYER 9_V5=TRUE|MID LAYER 10_V5=TRUE|MID LAYER 11_V5=TRUE|MID LAYER 12_V5=TRUE|MID LAYER 13_V5=TRUE|MID LAYER 14_V5=TRUE|MID LAYER 15_V5=TRUE|MID LAYER 16_V5=TRUE|MID LAYER 17_V5=TRUE|MID LAYER 18_V5=TRUE|MID LAYER 19_V5=TRUE|MID LAYER 20_V5=TRUE|MID LAYER 21_V5=TRUE|MID LAYER 22_V5=TRUE|MID LAYER 23_V5=TRUE|MID LAYER 24_V5=TRUE|MID LAYER 25_V5=TRUE|MID LAYER 26_V5=TRUE|MID LAYER 27_V5=TRUE|MID LAYER 28_V5=TRUE|MID LAYER 29_V5=TRUE|MID LAYER 30_V5=TRUE|BOTTOM LAYER_V5=TRUE<55>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingCorners|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingCorners|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=WPBQMRBU|DEFINEDBYLOGICALDOCUMENT=FALSE|CORNERSTYLE=45-Degree|MINSETBACK=100mil|MAXSETBACK=100mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=RoutingVias|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=RoutingVias|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=SCTBLHNM|DEFINEDBYLOGICALDOCUMENT=FALSE|HOLEWIDTH=7.874mil|WIDTH=17.7165mil|VIASTYLE=Through Hole|MINHOLEWIDTH=7.874mil|MINWIDTH=17.7165mil|MAXHOLEWIDTH=248.0315mil|MAXWIDTH=257.874mil<EFBFBD>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PlaneClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PlaneClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=SIVCUSVR|DEFINEDBYLOGICALDOCUMENT=FALSE|CLEARANCE=4mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SolderMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SolderMaskExpansion|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=MHLBVAUX|DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=2.9528mil<EFBFBD>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PasteMaskExpansion|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PasteMaskExpansion|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=HTVHRFGU|DEFINEDBYLOGICALDOCUMENT=FALSE|EXPANSION=0mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=ShortCircuit|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=ShortCircuit|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=IUYHWCJN|DEFINEDBYLOGICALDOCUMENT=FALSE|ALLOWED=FALSE<53>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=UnRoutedNet|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=UnRoutedNet|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=XYWQCYWI|DEFINEDBYLOGICALDOCUMENT=FALSE<53>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MinimumAnnularRing|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=MinimumAnnularRing|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=LTRQHDXK|DEFINEDBYLOGICALDOCUMENT=FALSE|MINIMUMRING=3mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=(InPadClass('PowerPads'))|NAME=PolygonConnectPowerPads|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=SOSFMGQU|DEFINEDBYLOGICALDOCUMENT=FALSE|CONNECTSTYLE=Direct|RELIEFCONDUCTORWIDTH=10mil|RELIEFENTRIES=4|POLYGONRELIEFANGLE=90 Angle|AIRGAPWIDTH=10mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=PolygonConnect|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=PolygonConnect|ENABLED=TRUE|PRIORITY=2|COMMENT= |UNIQUEID=HPMCAKLB|DEFINEDBYLOGICALDOCUMENT=FALSE|THPAD.CONNECTSTYLE=Relief|THPAD.RELIEFCONDUCTORWIDTH=4mil|THPAD.RELIEFENTRIES=4|THPAD.POLYGONRELIEFANGLE=90 Angle|THPAD.AIRGAPWIDTH=4mil|SMDPAD.CONNECTSTYLE=Relief|SMDPAD.RELIEFCONDUCTORWIDTH=4mil|SMDPAD.RELIEFENTRIES=4|SMDPAD.POLYGONRELIEFANGLE=90 Angle|SMDPAD.AIRGAPWIDTH=4mil|VIA.CONNECTSTYLE=Direct|VIA.RELIEFCONDUCTORWIDTH=5mil|VIA.RELIEFENTRIES=4|VIA.POLYGONRELIEFANGLE=90 Angle|VIA.AIRGAPWIDTH=5mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=ComponentClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=ComponentClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=HLSVBXXM|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=4mil|COLLISIONCHECKMODE=3|VERTICALGAP=4mil|SHOWDISTANCES=TRUE<55>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=HoleSize|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=HoleSize|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=QOCDLBEA|DEFINEDBYLOGICALDOCUMENT=FALSE|ABSOLUTEVALUES=TRUE|MAXLIMIT=248.0315mil|MINLIMIT=7.874mil|MAXPERCENT=80.000|MINPERCENT=20.000<EFBFBD>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FabricationTestpoint|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=FabricationTestpoint|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=KETBFYAH|DEFINEDBYLOGICALDOCUMENT=FALSE|SIDE=3|TESTPOINTUNDERCOMPONENT=TRUE|MINSIZE=40mil|MAXSIZE=100mil|PREFEREDSIZE=60mil|MINHOLESIZE=0mil|MAXHOLESIZE=40mil|PREFEREDHOLESIZE=32mil|TESTPOINTGRID=1mil|ALLOWSIDETOP=TRUE|ALLOWSIDEBOTTOM=TRUE|USEGRID=TRUE|GRIDTOLERANCE=0.01mil<EFBFBD>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FabricationTestPointUsage|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=FabricationTestPointUsage|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=BQUISTNE|DEFINEDBYLOGICALDOCUMENT=FALSE|VALID=0|ALLOWMULTIPLE=FALSE<53>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=LayerPairs|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=LayerPairs|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=IUQUOUXV|DEFINEDBYLOGICALDOCUMENT=FALSE|ENFORCE=TRUE<55>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsBGA|SCOPE2EXPRESSION=All|NAME=Fanout_BGA|ENABLED=TRUE|PRIORITY=1|COMMENT=Fanout_BGA (Default Rule)|UNIQUEID=MRKKSWNT|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsLCC|SCOPE2EXPRESSION=All|NAME=Fanout_LCC|ENABLED=TRUE|PRIORITY=2|COMMENT=Fanout_LCC (Default Rule)|UNIQUEID=QQXJWTOK|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsSOIC|SCOPE2EXPRESSION=All|NAME=Fanout_SOIC|ENABLED=TRUE|PRIORITY=3|COMMENT=Fanout_SOIC (Default Rule)|UNIQUEID=JBBELWPE|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=(CompPinCount < 5)|SCOPE2EXPRESSION=All|NAME=Fanout_Small|ENABLED=TRUE|PRIORITY=4|COMMENT=Fanout_Small (Default Rule)|UNIQUEID=DUBCFJYD|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=OutThenIn|VIAGRID=1mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=FanoutControl|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Fanout_Default|ENABLED=TRUE|PRIORITY=5|COMMENT=Fanout_Default (Default Rule)|UNIQUEID=YXKAIUTE|DEFINEDBYLOGICALDOCUMENT=FALSE|BGADIR=Out|BGAVIAMODE=Centered|FANOUTSTYLE=Auto|FANOUTDIRECTION=Alternating|VIAGRID=1mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=Height|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=Height|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=XLOOMPYH|DEFINEDBYLOGICALDOCUMENT=FALSE|MINHEIGHT=0mil|MAXHEIGHT=71497.9375mil|PREFHEIGHT=500mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=DiffPairsRouting|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=DiffPairsRouting|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=FFNGBKRQ|DEFINEDBYLOGICALDOCUMENT=FALSE|MAXLIMIT=4mil|MINLIMIT=4mil|MOSTFREQGAP=4mil|TOPLAYER_MINWIDTH=4mil|TOPLAYER_MAXWIDTH=71497.9375mil|TOPLAYER_PREFWIDTH=4mil|MIDLAYER1_MINWIDTH=4mil|MIDLAYER1_MAXWIDTH=71497.9375mil|MIDLAYER1_PREFWIDTH=4mil|MIDLAYER2_MINWIDTH=4mil|MIDLAYER2_MAXWIDTH=71497.9375mil|MIDLAYER2_PREFWIDTH=4mil|MIDLAYER3_MINWIDTH=4mil|MIDLAYER3_MAXWIDTH=71497.9375mil|MIDLAYER3_PREFWIDTH=4mil|MIDLAYER4_MINWIDTH=4mil|MIDLAYER4_MAXWIDTH=71497.9375mil|MIDLAYER4_PREFWIDTH=4mil|MIDLAYER5_MINWIDTH=4mil|MIDLAYER5_MAXWIDTH=71497.9375mil|MIDLAYER5_PREFWIDTH=4mil|MIDLAYER6_MINWIDTH=4mil|MIDLAYER6_MAXWIDTH=71497.9375mil|MIDLAYER6_PREFWIDTH=4mil|MIDLAYER7_MINWIDTH=4mil|MIDLAYER7_MAXWIDTH=71497.9375mil|MIDLAYER7_PREFWIDTH=4mil|MIDLAYER8_MINWIDTH=4mil|MIDLAYER8_MAXWIDTH=71497.9375mil|MIDLAYER8_PREFWIDTH=4mil|MIDLAYER9_MINWIDTH=4mil|MIDLAYER9_MAXWIDTH=71497.9375mil|MIDLAYER9_PREFWIDTH=4mil|MIDLAYER10_MINWIDTH=4mil|MIDLAYER10_MAXWIDTH=71497.9375mil|MIDLAYER10_PREFWIDTH=4mil|MIDLAYER11_MINWIDTH=4mil|MIDLAYER11_MAXWIDTH=71497.9375mil|MIDLAYER11_PREFWIDTH=4mil|MIDLAYER12_MINWIDTH=4mil|MIDLAYER12_MAXWIDTH=71497.9375mil|MIDLAYER12_PREFWIDTH=4mil|MIDLAYER13_MINWIDTH=4mil|MIDLAYER13_MAXWIDTH=71497.9375mil|MIDLAYER13_PREFWIDTH=4mil|MIDLAYER14_MINWIDTH=4mil|MIDLAYER14_MAXWIDTH=71497.9375mil|MIDLAYER14_PREFWIDTH=4mil|MIDLAYER15_MINWIDTH=4mil|MIDLAYER15_MAXWIDTH=71497.9375mil|MIDLAYER15_PREFWIDTH=4mil|MIDLAYER16_MINWIDTH=4mil|MIDLAYER16_MAXWIDTH=71497.9375mil|MIDLAYER16_PREFWIDTH=4mil|MIDLAYER17_MINWIDTH=4mil|MIDLAYER17_MAXWIDTH=71497.9375mil|MIDLAYER17_PREFWIDTH=4mil|MIDLAYER18_MINWIDTH=4mil|MIDLAYER18_MAXWIDTH=71497.9375mil|MIDLAYER18_PREFWIDTH=4mil|MIDLAYER19_MINWIDTH=4mil|MIDLAYER19_MAXWIDTH=71497.9375mil|MIDLAYER19_PREFWIDTH=4mil|MIDLAYER20_MINWIDTH=4mil|MIDLAYER20_MAXWIDTH=71497.9375mil|MIDLAYER20_PREFWIDTH=4mil|MIDLAYER21_MINWIDTH=4mil|MIDLAYER21_MAXWIDTH=71497.9375mil|MIDLAYER21_PREFWIDTH=4mil|MIDLAYER22_MINWIDTH=4mil|MIDLAYER22_MAXWIDTH=71497.9375mil|MIDLAYER22_PREFWIDTH=4mil|MIDLAYER23_MINWIDTH=4mil|MIDLAYER23_MAXWIDTH=71497.9375mil|MIDLAYER23_PREFWIDTH=4mil|MIDLAYER24_MINWIDTH=4mil|MIDLAYER24_MAXWIDTH=71497.9375mil|MIDLAYER24_PREFWIDTH=4mil|MIDLAYER25_MINWIDTH=4mil|MIDLAYER25_MAXWIDTH=71497.9375mil|MIDLAYER25_PREFWIDTH=4mil|MIDLAYER26_MINWIDTH=4mil|MIDLAYER26_MAXWIDTH=71497.9375mil|MIDLAYER26_PREFWIDTH=4mil|MIDLAYER27_MINWIDTH=4mil|MIDLAYER27_MAXWIDTH=71497.9375mil|MIDLAYER27_PREFWIDTH=4mil|MIDLAYER28_MINWIDTH=4mil|MIDLAYER28_MAXWIDTH=71497.9375mil|MIDLAYER28_PREFWIDTH=4mil|MIDLAYER29_MINWIDTH=4mil|MIDLAYER29_MAXWIDTH=71497.9375mil|MIDLAYER29_PREFWIDTH=4mil|MIDLAYER30_MINWIDTH=4mil|MIDLAYER30_MAXWIDTH=71497.9375mil|MIDLAYER30_PREFWIDTH=4mil|BOTTOMLAYER_MINWIDTH=4mil|BOTTOMLAYER_MAXWIDTH=71497.9375mil|BOTTOMLAYER_PREFWIDTH=4mil|MAXUNCOUPLEDLENGTH=500mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=HoleToHoleClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=HoleToHoleClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=KDLPQPYH|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=9.8425mil|ALLOWSTACKEDMICROVIAS=FALSE<53>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=MinimumSolderMaskSliver|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=MinimumSolderMaskSliver|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=HLLWTJBO|DEFINEDBYLOGICALDOCUMENT=FALSE|MINSOLDERMASKWIDTH=0mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SilkToSolderMaskClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=IsPad|SCOPE2EXPRESSION=All|NAME=SilkToSolderMaskClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=VXHXOYSJ|DEFINEDBYLOGICALDOCUMENT=FALSE|MINSILKSCREENTOMASKGAP=4mil|CLEARANCETOEXPOSEDCOPPER=TRUE<55>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=SilkToSilkClearance|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=SilkToSilkClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=LPWLVDIS|DEFINEDBYLOGICALDOCUMENT=FALSE|SILKTOSILKCLEARANCE=0mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=NetAntennae|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=NetAntennae|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=NCXUJVOQ|DEFINEDBYLOGICALDOCUMENT=FALSE|NETANTENNAETOLERANCE=0mil<69>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=AssemblyTestpoint|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=AssemblyTestpoint|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=QMHMVIFF|DEFINEDBYLOGICALDOCUMENT=FALSE|TESTPOINTUNDERCOMPONENT=TRUE|MINSIZE=40mil|MAXSIZE=100mil|PREFEREDSIZE=60mil|MINHOLESIZE=0mil|MAXHOLESIZE=40mil|PREFEREDHOLESIZE=32mil|TESTPOINTGRID=1mil|USEGRID=TRUE|GRIDTOLERANCE=0.01mil|ALLOWSIDETOP=TRUE|ALLOWSIDEBOTTOM=TRUE<55>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=AssemblyTestPointUsage|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=AssemblyTestPointUsage|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=KWLVDNGG|DEFINEDBYLOGICALDOCUMENT=FALSE<53>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=UnpouredPolygon|NETSCOPE=AnyNet|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=UnpouredPolygon|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=TAQTXOXB|DEFINEDBYLOGICALDOCUMENT=FALSE<53>
+SELECTION=FALSE|LAYER=TOP|LOCKED=FALSE|POLYGONOUTLINE=FALSE|USERROUTED=TRUE|KEEPOUT=FALSE|UNIONINDEX=0|RULEKIND=BoardOutlineClearance|NETSCOPE=DifferentNets|LAYERKIND=SameLayer|SCOPE1EXPRESSION=All|SCOPE2EXPRESSION=All|NAME=BoardOutlineClearance|ENABLED=TRUE|PRIORITY=1|COMMENT= |UNIQUEID=CDWUHYUL|DEFINEDBYLOGICALDOCUMENT=FALSE|GAP=7.874mil|GENERICCLEARANCE=7.874mil|IGNOREPADTOPADCLEARANCEINFOOTPRINT=FALSE|OBJECTCLEARANCES= <20>

dev/pcb/DESIGN_RULE_JLCPCB/JLC04121H-7628_1-2mm.csv

@@ -0,0 +1,23 @@
+Board Layer Stack
+Number;Name;Type;Manufacturer;Material;Process;Thickness (mm);Weight (oz);Dk;Df;Orientation;Copper Orientation;Description;Constructions;Resin (%);Frequency (GHz);GlassTransTemp (°C)
+;Top Overlay;Overlay;;;;;;;;;;;;;;
+;Top Solder;Solder Mask;;Solder Resist;;0.01;;3.8;;;;;;;;
+1;Top Layer;Signal;Altium Designer;Copper;ED;0.035;1;;;Top;Above;Copper Foil;;;;
+;Prepreg 1;Prepreg;Altium Designer;7628*1;;0.2104;;4.4;0.02;;;;7628;48;1;180
+2;Layer 1;Signal;Altium Designer;Copper;ED;0.0152;0.5;;;Not allowed;Above;Copper Foil;;;;
+;Core;Core;;Core;;0.6;;4.6;;;;;;;;
+3;Layer 2;Signal;Altium Designer;Copper;ED;0.0152;0.5;;;Not allowed;Below;Copper Foil;;;;
+;Prepreg 2;Prepreg;Altium Designer;7628*1;;0.2104;;4.4;0.02;;;;7628;48;1;180
+4;Bottom Layer;Signal;Altium Designer;Copper;ED;0.035;1;;;Bottom;Below;Copper Foil;;;;
+;Bottom Solder;Solder Mask;;Solder Resist;;0.01;;3.8;;;;;;;;
+;Bottom Overlay;Overlay;;;;;;;;;;;;;;
+
+
+No impedances
+
+Via types
+#;Name;Type;Layers;Stack
+1;Thru 1:4;Thru;Top Layer-Bottom Layer;Board Layer Stack
+
+
+No back drills