Firmware pin defintions mapped to pcb; checked 3d files, frontplates left/right ok (changes were made by me), housing supporting structure is mssing (middle), 3d file for connector part is missing

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [TRI-SQR-VCO_OTA_SS.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 14:24:51 On 11.12.2025
+Finished Output Generation At 14:45:26 On 03.02.2026

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/TRI-SQR-VCO_OTA_SS.nsx

@@ -1,5 +1,5 @@
 TRI-SQR-VCO_OTA_SS
-*SPICE Netlist generated by Advanced Sim server on 12.12.2025 14:46:42
+*SPICE Netlist generated by Advanced Sim server on 03.02.2026 15:26:41
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -22,38 +22,30 @@ XIC3B U_SAW NetIC3_6 VAP 0 NetIC3_7 TL074
 XIC3C VCM NetIC3_9 VAP 0 U_C TL074
 XIC3D VCM NetIC3_13 VAP 0 U_CV TL074
 XIC4A R.VMID NetIC4_1 VAP 0 NetIC4_1 TL074
-RPTC NetPTC_1 U_C 1k
 RR2 0 U_TRI 20k
 RR3 VAP NetIC1_1 15k
 RR4a NetIC3_2 U_TRI 200k
 RR4b U_in NetIC3_2 100k
 RR_Aa NetR_Aa_1 U_SQR_OTA 3.3k
 RR_Ab VCM NetR_Aa_1 330R
-RR_CV_a NetR_CV_a_1 U_CV 120k
-RR_CV_b NetR_CV_b_1 NetR_CV_a_1 6.8k
-RR_CV_c NetR_CV_b_1 NetIC3_9 820R
+RR_COARSEA 0 NetR_COARSE_2 {100k * {COARSE}}
+RR_COARSEB NetR_COARSE_2 VAP {100k - (100k * {COARSE})}
+RR_CV_a NetIC3_9 U_C 1k
+RR_CV_b NetR_COARSE_2 NetIC3_9 47k
+RR_CV_c U_CV NetIC3_9 47k
+RR_CV_d NetIC3_9 NetR_CV_d_2 1Meg
 RR_E NetC_an_2 NetR_E_2 10k
+RR_FINEA 0 NetR_CV_d_2 {100k * {FINE}}
+RR_FINEB NetR_CV_d_2 VAP {100k - (100k * {FINE})}
 RR_inv_a NetIC2_8 NetIC3_13 10k
 RR_inv_b NetIC3_13 U_CV 10k
-RR_lambda_T_a NetIC3_9 NetR_lambda_T_a_2 1.2k
-RR_lambda_T_b NetR_lambda_T_a_2 NetPTC_1 100R
 RR_off_b NetIC2_9 NetIC2_8 10k
-RR_off_c_+0 VAP NetR_off_c_+0_2 10k
-RR_off_c_+1A VAP NetR_off_c_+1_2 {8330R * 0.5}
-RR_off_c_+1B NetR_off_c_+1_2 NetR_off_c_+1_2 {8330R - (8330R * 0.5)}
-RR_off_c_+1_vor VAP NetR_off_c_+1_vor_2 10k
-RR_off_c_+2A VAP NetR_off_c_+2_2 {7150R * 0.5}
-RR_off_c_+2B NetR_off_c_+2_2 NetR_off_c_+2_2 {7150R - (7150R * 0.5)}
-RR_off_c_-1A NetR_off_c_+1_vor_2 NetR_off_c_-1_2 {2.5k * 0.5}
-RR_off_c_-1B NetR_off_c_-1_2 NetR_off_c_-1_2 {2.5k - (2.5k * 0.5)}
 RR_off_c_sim VAP NetIC2_9 10k
 RR_off_d NetR_off_d_1 NetIC2_9 10k
 RR_POT_refA 0 NetR_POT_ref_2 {100k * 0.5}
 RR_POT_refB NetR_POT_ref_2 NetR_POT_ref_2 {100k - (100k * 0.5)}
 RR_POT_SAWA 0 0 {10k * 0.5}
 RR_POT_SAWB 0 NetR_POT_SAW_3 {10k - (10k * 0.5)}
-RR_POT_uC_compA 0 NetR_POT_uC_comp_2 {100k * {Q}}
-RR_POT_uC_compB NetR_POT_uC_comp_2 VAP {100k - (100k * {Q})}
 RR_PWM_a1 NetR_POT_SAW_3 NetIC3_6 10k
 RR_PWM_a2 NetR_POT_SAW_3 NetIC3_6 10k
 RR_PWM_b NetIC3_6 VAP 10k
@@ -67,7 +59,6 @@ RR_SAW_b NetIC2_12 U_in 10k
 RR_SAW_c U_SAW NetIC2_13 10k
 RR_SAW_e U_SQR fet_gate 33k
 RR_SAW_f 0 fet_gate 100k
-RR_uC_comp NetIC3_9 NetR_POT_uC_comp_2 1Meg
 RRoff_a NetIC3_2 0 1Meg
 RRoff_b NetIC3_2 0 1Meg
 XT1 VCM NetC_an_2 NetC_an_1 U_C NetC_an_2 NetT1_6 DMMT3906W
@@ -96,7 +87,8 @@ SWEEP U_var LIST 0 1 2
 .ENDC
 
 *Global Parameters:
-.PARAM Q=0.5
+.PARAM COARSE={0.50}
+.PARAM FINE={0.3}
 
 *Models and Subcircuits:
 * A dual opamp ngspice model