Firmware pin defintions mapped to pcb; checked 3d files, frontplates left/right ok (changes were made by me), housing supporting structure is mssing (middle), 3d file for connector part is missing

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [VCA_LM13700.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 13:07:34 On 14.12.2025
+Finished Output Generation At 11:31:57 On 06.02.2026

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx

@@ -1,5 +1,5 @@
 VCA_LM13700
-*SPICE Netlist generated by Advanced Sim server on 14.12.2025 13:07:43
+*SPICE Netlist generated by Advanced Sim server on 06.02.2026 11:37:11
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -13,16 +13,19 @@ XIC1E NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1E_9
 + ExtraNet_XIC1E_10 VAP ExtraNet_XIC1E_12 ExtraNet_XIC1E_13 ExtraNet_XIC1E_14
 + ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
 RR1 NetIC1_14 IN 3.3k
-RR2 OUT VCM 27k
+RR2a OUT NetR2a_2 20k
+RR2b NetR2a_2 VCM 6.8k
 RR3 Uout 0 5.1k
 RR4 VCM NetIC1_14 1.2k
 RR5 VCM NetIC1_13 1.2k
 RR_B NetR_B_1 NetR_B_2 100k
 RR_BASE_GAIN NetIC1_16 NetR_BASE_GAIN_2 10k
 RR_D VAP NetIC1_15 5.1k
-QT VAP NetR_B_1 NetR_BASE_GAIN_2 QBC547B
+RR_GAINA NetR_BASE_GAIN_2 NetR_BASE_GAIN_2 {100k * {GAIN}}
+RR_GAINB NetR_BASE_GAIN_2 U_ABC {100k - (100k * {GAIN})}
+QT VAP NetR_B_1 U_ABC QBC547B
 VU_VCO_EN NetR_B_2 0 DC 0 PULSE(3.3 0 0 4u 1u 20m 40m) AC 1 0
-VUin IN VCM DC 0 SIN(0 2V 440Hz 0 0 0) AC 1 0
+VUin IN VCM DC 0 SIN(0 0 440Hz 0 0 0) AC 1 0
 VUneg VCM 0 +5V
 VUpos VAP VCM +5V
 
@@ -34,6 +37,7 @@ VUpos VAP VCM +5V
 .PLOT TRAN {i(R5)} =PLOT(6) =AXIS(1) =NAME(I_5) =UNITS(A)
 .PLOT TRAN {i(R4)} =PLOT(6) =AXIS(1) =NAME(I_4) =UNITS(A)
 .PLOT TRAN {2*(v(Uout)*0.663)} =PLOT(2) =AXIS(1) =NAME(Uout_buffer) =UNITS(V)
+.PLOT TRAN {v(U_ABC)} =PLOT(7) =AXIS(1) =NAME(U_ABC) =UNITS(V)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses: