Main schematic progress; checked VCA -> Voice Mixer compatibilty; DA Lib Update to V3.2

VCA-Voice Mixer checked if there might be a problem because of the offset, checked out to be ok after some minor fixes

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/TRI-SQR-VCO_OTA_SS.nsx

@@ -1,5 +1,5 @@
 TRI-SQR-VCO_OTA_SS
-*SPICE Netlist generated by Advanced Sim server on 11.12.2025 15:00:04
+*SPICE Netlist generated by Advanced Sim server on 12.12.2025 14:46:42
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -23,7 +23,7 @@ XIC3C VCM NetIC3_9 VAP 0 U_C TL074
 XIC3D VCM NetIC3_13 VAP 0 U_CV TL074
 XIC4A R.VMID NetIC4_1 VAP 0 NetIC4_1 TL074
 RPTC NetPTC_1 U_C 1k
-RR2 0 U_TRI 22k
+RR2 0 U_TRI 20k
 RR3 VAP NetIC1_1 15k
 RR4a NetIC3_2 U_TRI 200k
 RR4b U_in NetIC3_2 100k
@@ -38,13 +38,24 @@ RR_inv_b NetIC3_13 U_CV 10k
 RR_lambda_T_a NetIC3_9 NetR_lambda_T_a_2 1.2k
 RR_lambda_T_b NetR_lambda_T_a_2 NetPTC_1 100R
 RR_off_b NetIC2_9 NetIC2_8 10k
+RR_off_c_+0 VAP NetR_off_c_+0_2 10k
+RR_off_c_+1A VAP NetR_off_c_+1_2 {8330R * 0.5}
+RR_off_c_+1B NetR_off_c_+1_2 NetR_off_c_+1_2 {8330R - (8330R * 0.5)}
+RR_off_c_+1_vor VAP NetR_off_c_+1_vor_2 10k
+RR_off_c_+2A VAP NetR_off_c_+2_2 {7150R * 0.5}
+RR_off_c_+2B NetR_off_c_+2_2 NetR_off_c_+2_2 {7150R - (7150R * 0.5)}
+RR_off_c_-1A NetR_off_c_+1_vor_2 NetR_off_c_-1_2 {2.5k * 0.5}
+RR_off_c_-1B NetR_off_c_-1_2 NetR_off_c_-1_2 {2.5k - (2.5k * 0.5)}
 RR_off_c_sim VAP NetIC2_9 10k
 RR_off_d NetR_off_d_1 NetIC2_9 10k
 RR_POT_refA 0 NetR_POT_ref_2 {100k * 0.5}
 RR_POT_refB NetR_POT_ref_2 NetR_POT_ref_2 {100k - (100k * 0.5)}
-RR_POT_uC_compA NetR_POT_uC_comp_1 NetIC3_9 {1k * 0.5}
+RR_POT_SAWA 0 0 {10k * 0.5}
-RR_POT_uC_compB NetIC3_9 NetR_POT_uC_comp_3 {1k - (1k * 0.5)}
+RR_POT_SAWB 0 NetR_POT_SAW_3 {10k - (10k * 0.5)}
-RR_PWM_a 0 NetIC3_6 15k
+RR_POT_uC_compA 0 NetR_POT_uC_comp_2 {100k * {Q}}
+RR_POT_uC_compB NetR_POT_uC_comp_2 VAP {100k - (100k * {Q})}
+RR_PWM_a1 NetR_POT_SAW_3 NetIC3_6 10k
+RR_PWM_a2 NetR_POT_SAW_3 NetIC3_6 10k
 RR_PWM_b NetIC3_6 VAP 10k
 RR_PWM_c U_PWM NetIC3_7 10k
 RR_PWM_d VCM U_PWM 20k
@@ -56,8 +67,7 @@ RR_SAW_b NetIC2_12 U_in 10k
 RR_SAW_c U_SAW NetIC2_13 10k
 RR_SAW_e U_SQR fet_gate 33k
 RR_SAW_f 0 fet_gate 100k
-RR_uC_comp_GND 0 NetR_POT_uC_comp_1 330k
+RR_uC_comp NetIC3_9 NetR_POT_uC_comp_2 1Meg
-RR_uC_comp_VAP NetR_POT_uC_comp_3 VAP 330k
 RRoff_a NetIC3_2 0 1Meg
 RRoff_b NetIC3_2 0 1Meg
 XT1 VCM NetC_an_2 NetC_an_1 U_C NetC_an_2 NetT1_6 DMMT3906W
@@ -74,14 +84,20 @@ VU_var NetR_off_d_1 0 1
 .PLOT TRAN {v(U_PWM)} =PLOT(4) =AXIS(1) =NAME(U_PWM) =UNITS(V)
 .PLOT TRAN {i(U_MESSITOGND)} =PLOT(5) =AXIS(1) =NAME(I_GND) =UNITS(A)
 .PLOT TRAN {p(U_single)} =PLOT(6) =AXIS(1) =NAME(P_Supply) =UNITS(W)
+.PLOT TRAN {i(U_mess)} =PLOT(7) =AXIS(1) =NAME(I_ABC) =UNITS(A)
+.PLOT TRAN {v(U_C)} =PLOT(8) =AXIS(1) =NAME(U_C) =UNITS(V)
+.PLOT TRAN {v(U_CV)} =PLOT(9) =AXIS(1)
 
 .OPTIONS ABSTOL=1e-10 RELTOL=1e-2 VNTOL=1e-4 METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
 .TRAN 25u 20m 5m 25u
 .CONTROL
-SWEEP U_var LIST 1
+SWEEP U_var LIST 0 1 2
 .ENDC
 
+*Global Parameters:
+.PARAM Q=0.5
+
 *Models and Subcircuits:
 * A dual opamp ngspice model
 * file name: LM13700-DUAL.ckt

dev/analog/ETOTH-VOICE_MIXER/VOICE-MIXER/Project Outputs for VOICE-MIXER/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [VOICE-MIXER.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 14:35:22 On 10.09.2025
+Finished Output Generation At 17:19:12 On 13.12.2025

dev/analog/ETOTH-VOICE_MIXER/VOICE-MIXER/Project Outputs for VOICE-MIXER/VOICE-MIXER.nsx

@@ -1,16 +1,17 @@
 VOICE-MIXER
-*SPICE Netlist generated by Advanced Sim server on 10.09.2025 14:45:45
+*SPICE Netlist generated by Advanced Sim server on 14.12.2025 16:19:21
 .options MixedSimGenerated
 
 *Schematic Netlist:
-XIC1A 0 NetIC1_2 VCC VEE U_out TL074
+XIC1A VCM NetIC1_2 VAP 0 U_out TL074
-RR1 U_1 NetIC1_2 10k
+RR1 U_1 NetIC1_2 330k
-RR2 U_2 NetIC1_2 10k
+RR2 U_2 NetIC1_2 330k
-RR_K NetIC1_2 U_out 10k
+RR3 VAP NetIC1_2 620k
-VU_neg 0 VEE 12
+RR_K NetIC1_2 U_out 150k
-VU_pos VCC 0 12
+VU_neg VCM 0 5
-VU_sin1 U_1 0 DC 0 SIN(0 1 440 0 0 0) AC 1 0
+VU_pos VAP VCM 5
-VU_sin2 U_2 0 DC 0 SIN(0 1 880 0 0 0) AC 1 0
+VU_sin1 U_1 VCM DC 0 SIN(-1.3 2 440 0 0 0) AC 1 0
+VU_sin2 U_2 VCM DC 0 SIN(-1.3 2 440 0 0 0) AC 1 0
 
 .PLOT TRAN {v(U_out)} =PLOT(1) =AXIS(1) =NAME(U_out) =UNITS(V)
 .PLOT TRAN {v(U_1)} =PLOT(1) =AXIS(1) =NAME(U_1) =UNITS(V)

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [VCA_LM13700.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 13:14:07 On 06.12.2025
+Finished Output Generation At 13:07:34 On 14.12.2025

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx

@@ -1,5 +1,5 @@
 VCA_LM13700
-*SPICE Netlist generated by Advanced Sim server on 06.12.2025 16:21:09
+*SPICE Netlist generated by Advanced Sim server on 14.12.2025 13:07:43
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -12,17 +12,15 @@ XIC1C NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1C_9
 XIC1E NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1E_9
 + ExtraNet_XIC1E_10 VAP ExtraNet_XIC1E_12 ExtraNet_XIC1E_13 ExtraNet_XIC1E_14
 + ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
-RR1 NetIC1_14 IN 3k
+RR1 NetIC1_14 IN 3.3k
 RR2 OUT VCM 27k
 RR3 Uout 0 5.1k
-RR4 VCM NetIC1_14 1k
+RR4 VCM NetIC1_14 1.2k
-RR5 VCM NetIC1_13 1k
+RR5 VCM NetIC1_13 1.2k
 RR_B NetR_B_1 NetR_B_2 100k
 RR_BASE_GAIN NetIC1_16 NetR_BASE_GAIN_2 10k
-RR_D VAP NetIC1_15 5k
+RR_D VAP NetIC1_15 5.1k
-RR_GAINA NetR_BASE_GAIN_2 NetR_BASE_GAIN_2 {100k * {GAIN}}
+QT VAP NetR_B_1 NetR_BASE_GAIN_2 QBC547B
-RR_GAINB NetR_BASE_GAIN_2 NetR_GAIN_3 {100k - (100k * {GAIN})}
-QT VAP NetR_B_1 NetR_GAIN_3 QBC547B
 VU_VCO_EN NetR_B_2 0 DC 0 PULSE(3.3 0 0 4u 1u 20m 40m) AC 1 0
 VUin IN VCM DC 0 SIN(0 2V 440Hz 0 0 0) AC 1 0
 VUneg VCM 0 +5V
@@ -35,13 +33,11 @@ VUpos VAP VCM +5V
 .PLOT TRAN {ib(T)} =PLOT(5) =AXIS(1) =NAME(I_B) =UNITS(A)
 .PLOT TRAN {i(R5)} =PLOT(6) =AXIS(1) =NAME(I_5) =UNITS(A)
 .PLOT TRAN {i(R4)} =PLOT(6) =AXIS(1) =NAME(I_4) =UNITS(A)
+.PLOT TRAN {2*(v(Uout)*0.663)} =PLOT(2) =AXIS(1) =NAME(Uout_buffer) =UNITS(V)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
 .TRAN 45u 100m 20m 45u
-.CONTROL
-SWEEP GAIN 0 1 0.1
-.ENDC
 
 *Global Parameters:
 .PARAM GAIN={0.5}

dev/general/MainSys/EXT.Harness

@@ -0,0 +1,2 @@
+VCO_CTRL_1=OFFSET_SEL_PA,OFFSET_SEL_P1,OFFSET_SEL_P4,OFFSET_SEL_P7,OFFSET_SEL_P10,POT_FINE_A,POT_FINE_B,POT_IREF,POT_PWM_ADJ,IN_TRI,IN_SAW,IN_SQR,IN_PWM,OUT
+VCO_CTRL_2=OFFSET_SEL_PA,OFFSET_SEL_P1,OFFSET_SEL_P4,OFFSET_SEL_P7,OFFSET_SEL_P10,POT_FINE_A,POT_FINE_B,POT_IREF,POT_PWM_ADJ,IN_TRI,IN_SAW,IN_SQR,IN_PWM,OUT