Support strucuter of housing ok; missing 3d files: connnection, keyboard, rod and main

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [TRI-SQR-VCO_OTA_SS.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 14:24:51 On 11.12.2025
+Finished Output Generation At 14:45:26 On 03.02.2026

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/TRI-SQR-VCO_OTA_SS.nsx

@@ -1,5 +1,5 @@
 TRI-SQR-VCO_OTA_SS
-*SPICE Netlist generated by Advanced Sim server on 12.12.2025 14:46:42
+*SPICE Netlist generated by Advanced Sim server on 03.02.2026 15:26:41
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -22,38 +22,30 @@ XIC3B U_SAW NetIC3_6 VAP 0 NetIC3_7 TL074
 XIC3C VCM NetIC3_9 VAP 0 U_C TL074
 XIC3D VCM NetIC3_13 VAP 0 U_CV TL074
 XIC4A R.VMID NetIC4_1 VAP 0 NetIC4_1 TL074
-RPTC NetPTC_1 U_C 1k
 RR2 0 U_TRI 20k
 RR3 VAP NetIC1_1 15k
 RR4a NetIC3_2 U_TRI 200k
 RR4b U_in NetIC3_2 100k
 RR_Aa NetR_Aa_1 U_SQR_OTA 3.3k
 RR_Ab VCM NetR_Aa_1 330R
-RR_CV_a NetR_CV_a_1 U_CV 120k
-RR_CV_b NetR_CV_b_1 NetR_CV_a_1 6.8k
-RR_CV_c NetR_CV_b_1 NetIC3_9 820R
+RR_COARSEA 0 NetR_COARSE_2 {100k * {COARSE}}
+RR_COARSEB NetR_COARSE_2 VAP {100k - (100k * {COARSE})}
+RR_CV_a NetIC3_9 U_C 1k
+RR_CV_b NetR_COARSE_2 NetIC3_9 47k
+RR_CV_c U_CV NetIC3_9 47k
+RR_CV_d NetIC3_9 NetR_CV_d_2 1Meg
 RR_E NetC_an_2 NetR_E_2 10k
+RR_FINEA 0 NetR_CV_d_2 {100k * {FINE}}
+RR_FINEB NetR_CV_d_2 VAP {100k - (100k * {FINE})}
 RR_inv_a NetIC2_8 NetIC3_13 10k
 RR_inv_b NetIC3_13 U_CV 10k
-RR_lambda_T_a NetIC3_9 NetR_lambda_T_a_2 1.2k
-RR_lambda_T_b NetR_lambda_T_a_2 NetPTC_1 100R
 RR_off_b NetIC2_9 NetIC2_8 10k
-RR_off_c_+0 VAP NetR_off_c_+0_2 10k
-RR_off_c_+1A VAP NetR_off_c_+1_2 {8330R * 0.5}
-RR_off_c_+1B NetR_off_c_+1_2 NetR_off_c_+1_2 {8330R - (8330R * 0.5)}
-RR_off_c_+1_vor VAP NetR_off_c_+1_vor_2 10k
-RR_off_c_+2A VAP NetR_off_c_+2_2 {7150R * 0.5}
-RR_off_c_+2B NetR_off_c_+2_2 NetR_off_c_+2_2 {7150R - (7150R * 0.5)}
-RR_off_c_-1A NetR_off_c_+1_vor_2 NetR_off_c_-1_2 {2.5k * 0.5}
-RR_off_c_-1B NetR_off_c_-1_2 NetR_off_c_-1_2 {2.5k - (2.5k * 0.5)}
 RR_off_c_sim VAP NetIC2_9 10k
 RR_off_d NetR_off_d_1 NetIC2_9 10k
 RR_POT_refA 0 NetR_POT_ref_2 {100k * 0.5}
 RR_POT_refB NetR_POT_ref_2 NetR_POT_ref_2 {100k - (100k * 0.5)}
 RR_POT_SAWA 0 0 {10k * 0.5}
 RR_POT_SAWB 0 NetR_POT_SAW_3 {10k - (10k * 0.5)}
-RR_POT_uC_compA 0 NetR_POT_uC_comp_2 {100k * {Q}}
-RR_POT_uC_compB NetR_POT_uC_comp_2 VAP {100k - (100k * {Q})}
 RR_PWM_a1 NetR_POT_SAW_3 NetIC3_6 10k
 RR_PWM_a2 NetR_POT_SAW_3 NetIC3_6 10k
 RR_PWM_b NetIC3_6 VAP 10k
@@ -67,7 +59,6 @@ RR_SAW_b NetIC2_12 U_in 10k
 RR_SAW_c U_SAW NetIC2_13 10k
 RR_SAW_e U_SQR fet_gate 33k
 RR_SAW_f 0 fet_gate 100k
-RR_uC_comp NetIC3_9 NetR_POT_uC_comp_2 1Meg
 RRoff_a NetIC3_2 0 1Meg
 RRoff_b NetIC3_2 0 1Meg
 XT1 VCM NetC_an_2 NetC_an_1 U_C NetC_an_2 NetT1_6 DMMT3906W
@@ -96,7 +87,8 @@ SWEEP U_var LIST 0 1 2
 .ENDC
 
 *Global Parameters:
-.PARAM Q=0.5
+.PARAM COARSE={0.50}
+.PARAM FINE={0.3}
 
 *Models and Subcircuits:
 * A dual opamp ngspice model

dev/analog/Filter_Test/Project Outputs for Filter_Test/Filter_Test.nsx

@@ -1,5 +1,5 @@
 Filter_Test
-*SPICE Netlist generated by Advanced Sim server on 21.12.2025 21:14:32
+*SPICE Netlist generated by Advanced Sim server on 06.02.2026 11:30:06
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -50,22 +50,24 @@ RR_hilfe2 NetIC2_2 NetIC2_1 100k
 VU_mess_abc NetIC3_16 NetR_abc_2 0
 VU_mess_abc1 NetIC1_16 NetR_abc_2 0
 VU_mess_abc2 NetIC1_1 NetR_abc_2 0
-VUe Uin VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
+VUe Uin VCM DC 0 SIN(0 0 440Hz 0 0 0) AC 1 0
 VUneg VCM 0 +5V
 VUpos VAP VCM +5V
 
-.PLOT AC {dB(v(BP))} =PLOT(1) =AXIS(1) =NAME(Au_Uout) =UNITS(dB)
-.PLOT AC {dB(v(LP))} =PLOT(2) =AXIS(1) =NAME(Au_Uout2) =UNITS(dB)
-.PLOT AC {dB(v(HP))} =PLOT(3) =AXIS(1) =NAME(Au_HP) =UNITS(dB)
+.PLOT TRAN {v(div)} =PLOT(2) =AXIS(1) =NAME(div) =UNITS(V)
+.PLOT TRAN {i(U_mess_abc1)} =PLOT(3) =AXIS(1) =NAME(I_ABC1) =UNITS(A)
+.PLOT TRAN {i(U_mess_abc2)} =PLOT(3) =AXIS(1) =NAME(I_ABC2) =UNITS(A)
+.PLOT TRAN {i(U_mess_abc3)} =PLOT(3) =AXIS(1) =NAME(I_ABC3) =UNITS(A)
+.PLOT TRAN {v(Uin)} =PLOT(1) =AXIS(1) =NAME(U_E) =UNITS(V)
 
 *Selected Circuit Analyses:
-.AC DEC 50 20 20k
+.TRAN 90.91u 11.36m 0 90.91u
 .CONTROL
 SWEEP Q LIST 0.002 0.01 0.1 1
 .ENDC
 
 *Global Parameters:
-.PARAM Q=0.1
+.PARAM Q={0.1}
 
 *Models and Subcircuits:
 * A dual opamp ngspice model

dev/analog/Filter_Test/Project Outputs for Filter_Test/Status Report.Txt

@@ -0,0 +1,10 @@
+Output: Mixed Sim
+Type  : AdvSimNetlist
+From  : Project [Filter_Test.PrjPcb]
+   Generated File[Filter_Test.nsx]
+
+
+Files Generated   : 1
+Documents Printed : 0
+
+Finished Output Generation At 11:26:55 On 06.02.2026

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [VCA_LM13700.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 13:07:34 On 14.12.2025
+Finished Output Generation At 11:31:57 On 06.02.2026

dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx

@@ -1,5 +1,5 @@
 VCA_LM13700
-*SPICE Netlist generated by Advanced Sim server on 14.12.2025 13:07:43
+*SPICE Netlist generated by Advanced Sim server on 06.02.2026 11:37:11
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -13,16 +13,19 @@ XIC1E NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1E_9
 + ExtraNet_XIC1E_10 VAP ExtraNet_XIC1E_12 ExtraNet_XIC1E_13 ExtraNet_XIC1E_14
 + ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
 RR1 NetIC1_14 IN 3.3k
-RR2 OUT VCM 27k
+RR2a OUT NetR2a_2 20k
+RR2b NetR2a_2 VCM 6.8k
 RR3 Uout 0 5.1k
 RR4 VCM NetIC1_14 1.2k
 RR5 VCM NetIC1_13 1.2k
 RR_B NetR_B_1 NetR_B_2 100k
 RR_BASE_GAIN NetIC1_16 NetR_BASE_GAIN_2 10k
 RR_D VAP NetIC1_15 5.1k
-QT VAP NetR_B_1 NetR_BASE_GAIN_2 QBC547B
+RR_GAINA NetR_BASE_GAIN_2 NetR_BASE_GAIN_2 {100k * {GAIN}}
+RR_GAINB NetR_BASE_GAIN_2 U_ABC {100k - (100k * {GAIN})}
+QT VAP NetR_B_1 U_ABC QBC547B
 VU_VCO_EN NetR_B_2 0 DC 0 PULSE(3.3 0 0 4u 1u 20m 40m) AC 1 0
-VUin IN VCM DC 0 SIN(0 2V 440Hz 0 0 0) AC 1 0
+VUin IN VCM DC 0 SIN(0 0 440Hz 0 0 0) AC 1 0
 VUneg VCM 0 +5V
 VUpos VAP VCM +5V
 
@@ -34,6 +37,7 @@ VUpos VAP VCM +5V
 .PLOT TRAN {i(R5)} =PLOT(6) =AXIS(1) =NAME(I_5) =UNITS(A)
 .PLOT TRAN {i(R4)} =PLOT(6) =AXIS(1) =NAME(I_4) =UNITS(A)
 .PLOT TRAN {2*(v(Uout)*0.663)} =PLOT(2) =AXIS(1) =NAME(Uout_buffer) =UNITS(V)
+.PLOT TRAN {v(U_ABC)} =PLOT(7) =AXIS(1) =NAME(U_ABC) =UNITS(V)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:

dev/digital/Firmware_TEST/include/FIRMWARE_DEF.h

@@ -39,11 +39,11 @@
 #define PIN_SB_2_REC    35 // 35
 #define PIN_SB_2_PLAY   36 // 36
 // MISC/INFO PINS
-#define PIN_VCO1_EN     37 // PROD. pin 37 TODO: if there is an active key mapped to CV-Gate 1 --> HIGH
-#define PIN_VCO2_EN     38 // PROD. pin 38 TODO: if there is an active key mapped to CV-Gate 2 --> HIGH
-#define PIN_REC         39 // PROD. pin 39 TODO: if any sb is recording LED on (active-low)
+#define PIN_VCO1_EN     38 // PROD. pin 38 TODO: if there is an active key mapped to CV-Gate 1 --> HIGH
+#define PIN_VCO2_EN     39 // PROD. pin 39 TODO: if there is an active key mapped to CV-Gate 2 --> HIGH
+#define PIN_REC         37 // PROD. pin 37 TODO: if any sb is recording LED on (active-low)
 #define PIN_BPM         12 // PROD. pin 12 TODO: get bpm through potentiometer analog value -> ADC-Pin
-#define PIN_B_METRONOME 13 // PROD. pin 13 TODO: button activates/deactivates bpm led output (pull-up)
-#define PIN_L_METRONOME 14 // PROD. pin 14 TODO: led blinks according to bpm value (active-low)
+#define PIN_B_METRONOME 14 // PROD. pin 13 TODO: button activates/deactivates bpm led output (pull-up)
+#define PIN_L_METRONOME 13 // PROD. pin 14 TODO: led blinks according to bpm value (active-low)
 
 #endif

dev/digital/Firmware_TEST/src/FIRMWARE.cpp

@@ -209,7 +209,7 @@ void CV::setVoltage(uint8_t cvIndex, uint16_t mV)
 {
     if(cvIndex >= _nCV) return;
     MCP4728_channel_t ch = _cvChannelMap[cvIndex];
-    _dac->setChannelValue(ch, map(mV, 0, 2048, 0, 4095), MCP4728_VREF_INTERNAL);
+    _dac->setChannelValue(ch, map(mV, 0, 1992, 0, 2048), MCP4728_VREF_INTERNAL);
 }
 
 void CV::setVoltage(uint8_t cvIndex, Key k)

dev/digital/Firmware_TEST/src/main.cpp

@@ -14,11 +14,11 @@ Keyboard keyboard(N_KEYBOARD_ROW, N_KEYBOARD_COL, pins_keyboard_row, pins_keyboa
 Adafruit_MCP4728 MCP4728;
 MCP4728_channel_t cvMap[N_CV_GATES] = {MCP4728_CHANNEL_A, MCP4728_CHANNEL_B};
 uint16_t keyToVoltage[N_KEYBOARD_ROW*N_KEYBOARD_COL] = {
-    1*83,  6*83,  11*83, 16*83, 21*83,
-    2*83,  7*83,  12*83, 17*83, 22*83,
-    3*83,  8*83,  13*83, 18*83, 23*83,
-    4*83,  9*83,  14*83, 19*83, 24*83,
-    5*83,  10*83, 15*83, 20*83, 25*83
+     0*83,  1*83,  2*83,  3*83,  4*83,
+     5*83,  6*83,  7*83,  8*83,  9*83,
+    10*83, 11*83, 12*83, 13*83, 14*83,
+    15*83, 16*83, 17*83, 18*83, 19*83,
+    20*83, 21*83, 22*83, 23*83, 24*83
 };
 
 CV cv(&MCP4728, &Wire, N_CV_GATES, cvMap, keyToVoltage, N_KEYBOARD_ROW, N_KEYBOARD_COL);
@@ -48,7 +48,7 @@ static uint16_t last_voltage_ch2 = 0xFFFF;
 
 bool readButton(byte pin, ButtonState &state)
 {
-    bool reading = digitalRead(pin) == LOW;
+    bool reading = digitalRead(pin) == HIGH;
     bool buttonPressed = false;
     
     if(reading != state.last)
@@ -74,11 +74,11 @@ bool readButton(byte pin, ButtonState &state)
 
 void initButtons()
 {
-    pinMode(PIN_SB_1_REC, INPUT_PULLUP);
-    pinMode(PIN_SB_1_PLAY, INPUT_PULLUP);
-    pinMode(PIN_SB_2_REC, INPUT_PULLUP);
-    pinMode(PIN_SB_2_PLAY, INPUT_PULLUP);
-    pinMode(PIN_B_METRONOME, INPUT_PULLUP);
+    pinMode(PIN_SB_1_REC, INPUT_PULLDOWN);
+    pinMode(PIN_SB_1_PLAY, INPUT_PULLDOWN);
+    pinMode(PIN_SB_2_REC, INPUT_PULLDOWN);
+    pinMode(PIN_SB_2_PLAY, INPUT_PULLDOWN);
+    pinMode(PIN_B_METRONOME, INPUT_PULLDOWN);
     
     btn_sb1_rec.current = false;
     btn_sb1_rec.last = false;