Files
audio-synth/dev/general/MainSys/Project Logs for MainSys/CV_GEN SCH ECO 26.12.2025 22-49-56.LOG
Erik Tóth c661422a10 PCB WIP 2
All routing done, ready for review regarding the schematics, still have to do some silk screens...
2025-12-27 01:02:47 +01:00

6 lines
735 B
Plaintext

Replace Part C24 C TAJA106K016RNJ in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\CV_GEN.SchDoc with C TAJA106K016RNJ from DA_LIB.IntLib
Replace Part C25 C CL10B104KB8NNNC in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\CV_GEN.SchDoc with C CL10B104KB8NNNC from DA_LIB.IntLib
Replace Part IC7 IC MCP4728-E_UN in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\CV_GEN.SchDoc with IC MCP4728-E_UN from DA_LIB.IntLib
Replace Part R13 R 0402WGF1002TCE in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\CV_GEN.SchDoc with R 0402WGF1002TCE from DA_LIB.IntLib
Replace Part R14 R 0402WGF1002TCE in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\CV_GEN.SchDoc with R 0402WGF1002TCE from DA_LIB.IntLib