mirror of
https://github.com/erik-toth/audio-synth.git
synced 2025-12-06 10:40:02 +00:00
200 lines
6.5 KiB
Plaintext
200 lines
6.5 KiB
Plaintext
TRI-SQR-VCO_OTA
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*SPICE Netlist generated by Advanced Sim server on 18.07.2025 12:03:41
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.options MixedSimGenerated
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*Schematic Netlist:
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CC NetC_1 0 4.9645nF
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CC_an NetC_an_1 NetC_an_2 1nF
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XIC1A NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 VEE NetC_1 U_TRI ExtraNet_XIC1A_9
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+ ExtraNet_XIC1A_10 VCC U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
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XIC1B NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 VEE NetC_1 U_TRI ExtraNet_XIC1B_9
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+ ExtraNet_XIC1B_10 VCC U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
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XIC1C NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 VEE NetC_1 U_TRI ExtraNet_XIC1C_9
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+ ExtraNet_XIC1C_10 VCC U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
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XIC1E NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 VEE NetC_1 U_TRI ExtraNet_XIC1E_9
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+ ExtraNet_XIC1E_10 VCC U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
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XIC2A U_SQR_OTA U_SQR VCC VEE U_SQR TL074
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XIC2B 0 NetC_an_1 VCC VEE NetIC2_7 TL074
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XIC2C NetIC2_10 U_C VCC VEE U_C TL074
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RR2 VEE U_TRI 20k
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RR3 NetIC1_1 VCC 56k
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RR_A 0 U_SQR_OTA 4.7k
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RR_CV NetR_CV_1 NetIC2_10 59.941k
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RR_E NetC_an_2 NetR_E_2 20k
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RR_lambda_T NetIC2_10 0 1.1k
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RR_ref NetC_an_1 VEE 1.5Meg
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QT1 NetC_an_1 U_C NetC_an_2 2N2907
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QT2 NetT2_3 0 NetC_an_2 2N2907
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VU_mess NetT2_3 NetIC1_16 0
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VU_messref NetR_E_2 NetIC2_7 0
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VU_neg 0 VEE 15
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VU_pos VCC 0 15
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VU_var NetR_CV_1 0 1
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.PLOT TRAN {v(U_SQR)} =PLOT(2) =AXIS(1) =NAME(U_SQR) =UNITS(V)
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.PLOT TRAN {v(U_TRI)} =PLOT(1) =AXIS(1) =NAME(U_TRI) =UNITS(V)
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.PLOT TRAN {v(U_SQR_OTA)-v(U_TRI)} =PLOT(3) =AXIS(1) =NAME(Delta-V @ OTA-B) =UNITS(V)
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.PLOT TRAN {v(R_lambda_T)} =PLOT(4) =AXIS(1) =NAME(U_lambda_T) =UNITS(V)
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.PLOT TRAN {i(U_mess)} =PLOT(5) =AXIS(1) =NAME(I_ABC) =UNITS(A)
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.PLOT TRAN {v(U_C)} =PLOT(4) =AXIS(1) =NAME(U_C) =UNITS(V)
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.PLOT TRAN {i(U_messref)} =PLOT(5) =AXIS(1) =NAME(I_ref + I_ABC) =UNITS(A)
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.OPTIONS ITL4=100 METHOD=GEAR MAXORD=2
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*Selected Circuit Analyses:
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.TRAN 1u 16m 10m 1u UIC
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.CONTROL
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SWEEP R_ref LIST 1.6905Meg U_var LIST 1.08333
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.ENDC
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*Models and Subcircuits:
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* A dual opamp ngspice model
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* file name: LM13700-DUAL.ckt
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.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
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+ 2out 2in- 2in+ 2Dbias 2ABin
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*//////////////////////////////////////////////////////////////////////
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* (C) National Semiconductor, Inc.
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* Models developed and under copyright by:
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* National Semiconductor, Inc.
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*/////////////////////////////////////////////////////////////////////
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* Legal Notice: This material is intended for free software support.
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* The file may be copied, and distributed; however, reselling the
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* material is illegal
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*////////////////////////////////////////////////////////////////////
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* For ordering or technical information on these models, contact:
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* National Semiconductor's Customer Response Center
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* 7:00 A.M.--7:00 P.M. U.S. Central Time
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* (800) 272-9959
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* For Applications support, contact the Internet address:
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* amps-apps@galaxy.nsc.com
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* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
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* LM13700 Dual Operational Transconductance Amplifier
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* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
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*
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* Amplifier Bias Input
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* | Diode Bias
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* | | Positive Input
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* | | | Negative Input
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* | | | | Output
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* | | | | | Negative power supply
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* | | | | | | Buffer Input
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* | | | | | | | Buffer Output
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* | | | | | | | | Positive power supply
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* | | | | | | | | |
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.SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11
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*
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* Features:
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* gm adjustable over 6 decades.
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* Excellent gm linearity.
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* Linearizing diodes.
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* Wide supply range of +/-2V to +/-22V.
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*
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* Note: This model is single-pole in nature and over-estimates
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* AC bandwidth and phase margin (stability) by over 2X.
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* Although refinement may be possible in the future, please
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* use benchtesting to finalize AC circuit design.
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*
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* Note: Model is for single device only and simulated
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* supply current is 1/2 of total device current.
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*
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******************************************************
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*
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C1 6 4 4.8P
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C2 3 6 4.8P
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* Output capacitor
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C3 5 6 6.26P
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D1 2 4 DX
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D2 2 3 DX
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D3 11 21 DX
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D4 21 22 DX
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D5 1 26 DX
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D6 26 27 DX
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D7 5 29 DX
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D8 28 5 DX
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D10 31 25 DX
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* Clamp for -CMR
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D11 28 25 DX
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* Ios source
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F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9
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F2 11 5 V2 1.022
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F3 25 6 V3 1.0
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F4 5 6 V1 1.022
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* Output impedance
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F5 5 0 POLY(2) V3 V7 0 0 0 0 1
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G1 0 33 5 0 .55E-3
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I1 11 6 300U
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Q1 24 32 31 QX1
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Q2 23 3 31 QX2
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Q3 11 7 30 QZ
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Q4 11 30 8 QY
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V1 22 24 0V
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V2 22 23 0V
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V3 27 6 0V
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V4 11 29 1.4
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V5 28 6 1.2
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V6 4 32 0V
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V7 33 0 0V
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.MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
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.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
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.MODEL QY NPN (IS=6E-15 BF=50)
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.MODEL QZ NPN (IS=5E-16 BF=266)
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.MODEL DX D (IS=5E-16)
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.ENDS
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*$
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XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
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XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
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.ends
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*TL074
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*Quad LoNoise JFETInput OpAmp pkg:DIP14
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*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
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* Connections:
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* Non-Inverting Input
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* | Inverting Input
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* | | Positive Power Supply
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* | | | Negative Power Supply
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* | | | | Output
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* | | | | |
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.SUBCKT TL074 1 2 3 4 5
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C1 11 12 3.498E-12
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C2 6 7 15E-12
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DC 5 53 DX
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DE 54 5 DX
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DLP 90 91 DX
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DLN 92 90 DX
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DP 4 3 DX
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BGND 99 0 V=V(3)*.5 + V(4)*.5
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BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
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+ I(VLP)*5E6 - I(VLN)*5E6
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GA 6 0 11 12 282.8E-6
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GCM 0 6 10 99 8.942E-9
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ISS 3 10 DC 195E-6
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HLIM 90 0 VLIM 1K
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J1 11 2 10 JX
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J2 12 1 10 JX
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R2 6 9 100E3
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RD1 4 11 3.536E3
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RD2 4 12 3.536E3
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RO1 8 5 150
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RO2 7 99 150
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RP 3 4 2.143E3
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RSS 10 99 1.026E6
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VB 9 0 DC 0
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VC 3 53 DC 2.2
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VE 54 4 DC 2.2
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VLIM 7 8 DC 0
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VLP 91 0 DC 25
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VLN 0 92 DC 25
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.MODEL DX D(IS=800E-18)
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.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
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.ENDS TL074
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*2N2907 MCE 5-27-97
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*Ref: Motorola Small-Signal Device databook, Q4/94
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*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
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.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
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+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
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+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
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.END |