Files
audio-synth/dev/general/MainSys/Project Logs for MainSys/MAIN PCB ECO 26.12.2025 17-25-44.LOG
Erik Tóth c661422a10 PCB WIP 2
All routing done, ready for review regarding the schematics, still have to do some silk screens...
2025-12-27 01:02:47 +01:00

11 lines
699 B
Plaintext

Removed Pin From Net: NetName=CV_1 Pin=R41_1-2
Removed Pin From Net: NetName=CV_2 Pin=R41_2-2
Added Component: Designator=C31(CAP-TH_RD_D-5_L-11_P-2.5)
Add component (AddParameter): Name = "CAuthor"; Value = "Erik Tóth"; VariantName = "[No Variations]"
Add component (AddParameter): Name = "LatestRev"; Value = "2025-12-26"; VariantName = "[No Variations]"
Add component (AddParameter): Name = "Published"; Value = "2025-12-26"; VariantName = "[No Variations]"
Add component (AddParameter): Name = "Value"; Value = "100uF"; VariantName = "[No Variations]"
Added Pin To Net: NetName=VAP Pin=C31-1
Added Pin To Net: NetName=GND Pin=C31-2
Added Member To Class: ClassName=OS Member=Component C31 100uF