mirror of
https://github.com/erik-toth/audio-synth.git
synced 2025-12-13 07:50:02 +00:00
Corretion on project_sim
This commit is contained in:
@@ -7,4 +7,4 @@ From : Project [TRI-SQR-VCO_OTA_SS.PrjPcb]
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Files Generated : 1
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Documents Printed : 0
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Finished Output Generation At 15:12:22 On 09.12.2025
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Finished Output Generation At 14:24:51 On 11.12.2025
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@@ -1,9 +1,5 @@
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TRI-SQR-VCO_OTA_SS
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<<<<<<< HEAD
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*SPICE Netlist generated by Advanced Sim server on 08.12.2025 23:07:23
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=======
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*SPICE Netlist generated by Advanced Sim server on 09.12.2025 15:13:04
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>>>>>>> 4c50a877b8fab4acd4165c9df592fd3d2535cd18
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*SPICE Netlist generated by Advanced Sim server on 11.12.2025 15:00:04
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.options MixedSimGenerated
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*Schematic Netlist:
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@@ -25,11 +21,7 @@ XIC3A VCM NetIC3_2 VAP 0 U_in TL074
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XIC3B U_SAW NetIC3_6 VAP 0 NetIC3_7 TL074
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XIC3C VCM NetIC3_9 VAP 0 U_C TL074
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XIC3D VCM NetIC3_13 VAP 0 U_CV TL074
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<<<<<<< HEAD
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XIC4A R.VMID NetIC4_1 VAP 0 NetIC4_1 TL074
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=======
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XICSA R.VMID NetICS_2 VAP 0 NetICS_6 TL071
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>>>>>>> 4c50a877b8fab4acd4165c9df592fd3d2535cd18
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RPTC NetPTC_1 U_C 1k
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RR2 0 U_TRI 22k
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RR3 VAP NetIC1_1 15k
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@@ -41,25 +33,24 @@ RR_CV_a NetR_CV_a_1 U_CV 120k
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RR_CV_b NetR_CV_b_1 NetR_CV_a_1 6.8k
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RR_CV_c NetR_CV_b_1 NetIC3_9 820R
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RR_E NetC_an_2 NetR_E_2 10k
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RR_inv_a NetIC2_8 NetIC3_13 1k
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RR_inv_b NetIC3_13 U_CV 1k
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RR_inv_a NetIC2_8 NetIC3_13 10k
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RR_inv_b NetIC3_13 U_CV 10k
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RR_lambda_T_a NetIC3_9 NetR_lambda_T_a_2 1.2k
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RR_lambda_T_b NetR_lambda_T_a_2 NetPTC_1 100R
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RR_off_b NetIC2_9 NetIC2_8 1k
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RR_off_c_sim VAP NetIC2_9 1k
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RR_off_d NetR_off_d_1 NetIC2_9 1k
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RR_off_b NetIC2_9 NetIC2_8 10k
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RR_off_c_sim VAP NetIC2_9 10k
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RR_off_d NetR_off_d_1 NetIC2_9 10k
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RR_POT_refA 0 NetR_POT_ref_2 {100k * 0.5}
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RR_POT_refB NetR_POT_ref_2 NetR_POT_ref_2 {100k - (100k * 0.5)}
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RR_POT_uC_compA NetR_POT_uC_comp_1 NetIC3_9 {1k * 0.5}
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RR_POT_uC_compB NetIC3_9 NetR_POT_uC_comp_3 {1k - (1k * 0.5)}
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RR_PWM_a 0 NetIC3_6 15k
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RR_PWM_b NetIC3_6 VAP 10k
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RR_PWM_c U_PWM NetIC3_7 1k
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RR_PWM_d NetR_PWM_d_1 U_PWM 1k
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RR_PWM_e VCM NetR_PWM_d_1 1k
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RR_PWM_c U_PWM NetIC3_7 10k
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RR_PWM_d VCM U_PWM 20k
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RR_ref NetC_an_1 NetR_POT_ref_2 470k
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RR_S1 R.VMID VAP 220k
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RR_S2 0 R.VMID 220k
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RR_S1 R.VMID VAP 510k
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RR_S2 0 R.VMID 510k
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RR_SAW_a NetIC2_13 U_in 10k
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RR_SAW_b NetIC2_12 U_in 10k
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RR_SAW_c U_SAW NetIC2_13 10k
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@@ -71,15 +62,8 @@ RRoff_a NetIC3_2 0 1Meg
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RRoff_b NetIC3_2 0 1Meg
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XT1 VCM NetC_an_2 NetC_an_1 U_C NetC_an_2 NetT1_6 DMMT3906W
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JT_SAW VCM fet_gate NetIC2_12 BF256B
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<<<<<<< HEAD
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VU_mess NetT2_3 NetIC1_16 0
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VU_MESSITOGND NetIC4_1 VCM 0
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=======
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QTS1 VAP NetICS_6 NetICS_2 2N2222
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QTS2 0 NetICS_6 NetICS_2 2N2907
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VU_mess NetT1_6 NetIC1_16 0
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VU_MESSITOGND NetICS_2 VCM 0
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>>>>>>> 4c50a877b8fab4acd4165c9df592fd3d2535cd18
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VU_MESSITOGND NetIC4_1 VCM 0
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VU_messref NetR_E_2 NetIC2_7 0
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VU_single VAP 0 +10V
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VU_var NetR_off_d_1 0 1
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@@ -88,12 +72,15 @@ VU_var NetR_off_d_1 0 1
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.PLOT TRAN {v(U_TRI)} =PLOT(2) =AXIS(1) =NAME(U_TRI) =UNITS(V)
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.PLOT TRAN {v(U_SAW)} =PLOT(3) =AXIS(1) =NAME(U_SAW) =UNITS(V)
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.PLOT TRAN {v(U_PWM)} =PLOT(4) =AXIS(1) =NAME(U_PWM) =UNITS(V)
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.PLOT TRAN {v(fet_gate)} =PLOT(5) =AXIS(1) =NAME(fet_gate) =UNITS(V)
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.PLOT TRAN {v(U_in)} =PLOT(6) =AXIS(1)
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.PLOT TRAN {i(U_MESSITOGND)} =PLOT(5) =AXIS(1) =NAME(I_GND) =UNITS(A)
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.PLOT TRAN {p(U_single)} =PLOT(6) =AXIS(1) =NAME(P_Supply) =UNITS(W)
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.OPTIONS ABSTOL=1e-10 RELTOL=1e-2 VNTOL=1e-4 METHOD=GEAR MAXORD=2
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*Selected Circuit Analyses:
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.TRAN 20u 20m 5m 20u
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.TRAN 25u 20m 5m 25u
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.CONTROL
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SWEEP U_var LIST 1
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.ENDC
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*Models and Subcircuits:
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* A dual opamp ngspice model
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@@ -239,57 +226,6 @@ VLN 0 92 DC 25
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.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
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.ENDS TL074
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<<<<<<< HEAD
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*2N2907 MCE 5-27-97
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*Ref: Motorola Small-Signal Device databook, Q4/94
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*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
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.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
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+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
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+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
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=======
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*TL071
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*Sngl LoNoise JFETInput OpAmp pkg:DIP8 3,2,7,4,6
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* Connections:
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* Non-Inverting Input
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* | Inverting Input
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* | | Positive Power Supply
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* | | | Negative Power Supply
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* | | | | Output
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* | | | | |
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.SUBCKT TL071 1 2 3 4 5
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C1 11 12 3.498E-12
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C2 6 7 15E-12
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DC 5 53 DX
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DE 54 5 DX
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DLP 90 91 DX
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DLN 92 90 DX
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DP 4 3 DX
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BGND 99 0 V=V(3)*.5 + V(4)*.5
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BB 7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
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+ I(VLP)*5E6 - I(VLN)*5E6
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GA 6 0 11 12 282.8E-6
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GCM 0 6 10 99 8.942E-9
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ISS 3 10 DC 195E-6
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HLIM 90 0 VLIM 1K
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J1 11 2 10 JX
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J2 12 1 10 JX
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R2 6 9 100E3
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RD1 4 11 3.536E3
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RD2 4 12 3.536E3
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RO1 8 5 150
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RO2 7 99 150
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RP 3 4 2.143E3
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RSS 10 99 1.026E6
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VB 9 0 DC 0
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VC 3 53 DC 2.2
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VE 54 4 DC 2.2
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VLIM 7 8 DC 0
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VLP 91 0 DC 25
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VLN 0 92 DC 25
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.MODEL DX D(IS=800E-18)
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.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
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.ENDS TL071
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*SRC=DMMT3906W;DI_DMMT3906W;BJTs PNP; Si; 40.0V 0.200A 257MHz Diodes, Inc. PNP
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.MODEL DI_DMMT3906W PNP (IS=20.3f NF=1.00 BF=274 VAF=114
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+ IKF=36.4m ISE=6.99p NE=2.00 BR=4.00 NR=1.00
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@@ -301,7 +237,6 @@ VLN 0 92 DC 25
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Q1 C1 B1 E1 DI_DMMT3906W
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Q2 C2 B2 E2 DI_DMMT3906W
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.ENDS DMMT3906W
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>>>>>>> 4c50a877b8fab4acd4165c9df592fd3d2535cd18
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*PHILIPS SEMICONDUCTORS Version: 1.0
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*Filename: bf256a_bf256b_philips
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@@ -320,18 +255,4 @@ Q2 C2 B2 E2 DI_DMMT3906W
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+ FC = 5.00000E-001
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+)
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*2N2222 MCE 5-20-97
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*Ref: Motorola Small-Signal Device Databook, Q4/94
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*Si 400mW 30V 800mA 300MHz GenPurp pkg:TO-18 3,2,1
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.MODEL 2N2222 NPN (IS=81.2F NF=1 BF=195 VAF=98.6 IKF=0.48 ISE=53.7P NE=2
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+ BR=4 NR=1 VAR=20 IKR=0.72 RE=64.4M RB=0.258 RC=25.8M XTB=1.5
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+ CJE=89.5P VJE=1.1 MJE=0.5 CJC=28.9P VJC=0.3 MJC=0.3 TF=530P TR=368N)
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*2N2907 MCE 5-27-97
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*Ref: Motorola Small-Signal Device databook, Q4/94
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*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
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.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
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+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
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+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
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.END
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