Output Stage Update

Schaltung neu aufgebaut, neu simuliert, bei Erik mit Analog Discovery überprüft, OK

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/ETOTH-Amp_LM386.nsx

@@ -1,98 +1,32 @@
 ETOTH-Amp_LM386
-*SPICE Netlist generated by Advanced Sim server on 21.11.2025 08:22:05
+*SPICE Netlist generated by Advanced Sim server on 25.11.2025 22:45:08
 .options MixedSimGenerated
 
 *Schematic Netlist:
-CC1 NetC1_1 NetC1_2 47nF
-CC_VCM1 NetC_VCM1_1 GND 47uF
-CC_VCM2 VAP NetC_VCM1_1 47uF
-CCblock NetC1_2 NetCblock_2 220uF
-CCblock1 NetCblock1_1 NetCblock1_2 47uF
-XIC1C NetIC1_10 NetC_VCM1_1 VAP GND NetIC1_8 TL074
-XIC2 NetIC2_1 GND NetCblock1_2 GND NetC1_2 VAP NetIC2_7 NetIC2_8 LM386
-LL_Speaker GND NetL_Speaker_2 0.1mH
-RR1 NetC1_1 GND 10R
+CCblock NetCblock_1 OUT 220uF
+CCblock1 NetCblock1_1 NetCblock1_2 10nF
+XIC1A NetIC1_1 0 NetCblock1_2 0 NetCblock_1 VAP NetIC1_7 NetIC1_8 lm386
+XIC1B NetIC1_1 0 NetCblock1_2 0 NetCblock_1 VAP NetIC1_7 NetIC1_8 lm386
+LL_Speaker 0 NetL_Speaker_2 0.1mH
 RR_POTA 0 NetR_POT_2 {10k * {POS}}
-RR_POTB NetR_POT_2 NetR_POT_3 {10k - (10k * {POS})}
-RR_rs1 NetIC1_10 VAP 470k
-RR_rs2 GND NetIC1_10 470k
-RR_Speaker NetL_Speaker_2 NetCblock_2 8R
-RR_static1 NetCblock1_1 NetR_POT_2 9400R
-RR_static2 0 NetCblock1_1 600R
-QT_rsN GND NetIC1_8 NetC_VCM1_1 2N2907
-QT_rsP VAP NetIC1_8 NetC_VCM1_1 2N2222
-VU_q VAP GND 10V
-VU_VCM_CURRENT 0 NetC_VCM1_1 0
-VUin NetR_POT_3 0 DC 0 SIN(0 2 440Hz 0 0 0) AC 1 0
+RR_POTB NetR_POT_2 IN {10k - (10k * {POS})}
+RR_Speaker NetL_Speaker_2 OUT 8R
+RR_static1 NetCblock1_1 NetR_POT_2 100k
+RR_static2 0 NetCblock1_1 10k
+VU_q VAP 0 10V
+VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
 
-.PLOT TRAN {v(R_Speaker)+v(L_Speaker)} =PLOT(1) =AXIS(1) =NAME(U_speaker) =UNITS(V) =RGB(0, 255, 0)
-.PLOT TRAN {i(R_Speaker)} =PLOT(2) =AXIS(1) =NAME(I_speaker) =UNITS(A)
-.PLOT TRAN {p(R_Speaker)} =PLOT(3) =AXIS(1) =NAME(P_speaker) =UNITS(W)
-.PLOT TRAN {i(U_VCM_CURRENT)} =PLOT(4) =AXIS(1) =NAME(I_VCM) =UNITS(A)
-.PLOT TRAN {v(VAP)} =PLOT(1) =AXIS(1) =RGB(255, 0, 0)
-.PLOT TRAN {v(GND)} =PLOT(1) =AXIS(1) =RGB(0, 0, 255)
-.PLOT TRAN {i(Cblock1)} =PLOT(5) =AXIS(1) =NAME(I_C_in) =UNITS(A)
-.PLOT TRAN {v(Cblock1)} =PLOT(5) =AXIS(2) =NAME(U_C_in) =UNITS(V)
-.PLOT TRAN {i(Cblock1)} =PLOT(5) =AXIS(1) =NAME(I_C_out) =UNITS(A)
-.PLOT TRAN {v(Cblock1)} =PLOT(5) =AXIS(2) =NAME(U_C_out) =UNITS(V)
+.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255)
+.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
-.TRAN 45.45u 22.73m 0 45.45u
+.TRAN 90.91u 22.73m 0 90.91u
 
 *Global Parameters:
 .PARAM POS={1}
 
 *Models and Subcircuits:
-*TL074
-*Quad LoNoise JFETInput OpAmp pkg:DIP14
-*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
-* Connections:
-*             Non-Inverting Input
-*             | Inverting Input
-*             | | Positive Power Supply
-*             | | | Negative Power Supply
-*             | | | | Output
-*             | | | | |
-.SUBCKT TL074 1 2 3 4 5
-C1   11 12 3.498E-12
-C2    6  7 15E-12
-DC    5 53 DX
-DE   54  5 DX
-DLP  90 91 DX
-DLN  92 90 DX
-DP    4  3 DX
-BGND 99  0 V=V(3)*.5 + V(4)*.5
-BB    7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
-+              I(VLP)*5E6 - I(VLN)*5E6
-GA    6  0 11 12 282.8E-6
-GCM   0  6 10 99 8.942E-9
-ISS   3 10 DC 195E-6
-HLIM 90  0 VLIM 1K
-J1   11  2 10 JX
-J2   12  1 10 JX
-R2    6  9 100E3
-RD1   4 11 3.536E3
-RD2   4 12 3.536E3
-RO1   8  5 150
-RO2   7 99 150
-RP    3  4 2.143E3
-RSS  10 99 1.026E6
-VB    9  0 DC 0
-VC    3 53 DC 2.2
-VE   54  4 DC 2.2
-VLIM  7  8 DC 0
-VLP  91  0 DC 25
-VLN   0 92 DC 25
-.MODEL DX D(IS=800E-18)
-.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
-.ENDS TL074
-
-*TopSPICE library: Models\MISCSEMI.MDB
-*PART NUMBER: LM386
-*MODEL NAME:  LM386
-*SYMBOL:      X8PIN
-*
 *LM386 Audio power amplifier
 * /*
 * 1.  The following model behavior shows good agreement with the
@@ -103,9 +37,9 @@ VLN   0 92 DC 25
 *   c) Power-supply rejection ratio, both bypassed and unbypassed;
 *   d) Voltage gain, both with pins 1&8 shorted and open; and
 *   e) Total harmonic distortion.
-* 
+*
 * 2.  The model has the following discrepancies:
-* 
+*
 *   f) High-gain frequency response looks somewhat more wideband
 *      than the actual device;
 *   g) Peak-to-peak output voltage swing is a bit more than the
@@ -114,13 +48,13 @@ VLN   0 92 DC 25
 *   h) Input bias current in this model is only about 7 nA,
 *      compared with the 250 nA "typical" value mentioned in
 *      the data sheet.
-* 
+*
 * 3.  The frequency response characteristics of this LM386 model
 * can be adjusted somewhat by changing C1, the rolloff capacitor in
 * the voltage gain stage.  It could also be made more realistic by
 * tweaking transistor model parameters Cjc, Cje, Tr and Tf,
 * although this can get pretty hairy.
-* 
+*
 * 4.  Likewise, output drive capability could be made more
 * realistic by tweaking transistor model parameters; again, this is
 * hairy.
@@ -174,18 +108,4 @@ q14 out 10018 gnd ddnpn 100
 + Tf=1n Itf=1 Xtf=0 Vtf=10)
 .ends LM386
 
-*2N2907 MCE 5-27-97
-*Ref: Motorola Small-Signal Device databook, Q4/94
-*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
-.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
-+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
-+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
-
-*2N2222 MCE 5-20-97
-*Ref: Motorola Small-Signal Device Databook, Q4/94
-*Si 400mW 30V 800mA 300MHz GenPurp pkg:TO-18 3,2,1
-.MODEL 2N2222 NPN (IS=81.2F NF=1 BF=195 VAF=98.6 IKF=0.48 ISE=53.7P NE=2
-+ BR=4 NR=1 VAR=20 IKR=0.72 RE=64.4M RB=0.258 RC=25.8M XTB=1.5
-+ CJE=89.5P VJE=1.1 MJE=0.5 CJC=28.9P VJC=0.3 MJC=0.3 TF=530P TR=368N)
-
 .END

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [ETOTH-Amp_LM386.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 08:00:57 On 21.11.2025
+Finished Output Generation At 22:41:52 On 25.11.2025