DA Library Update V3.1

diverse R, C, T, sonstige Normaliserungen

dev/analog/.gitignore

@@ -0,0 +1 @@
+**/History

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/ETOTH-Amp_LM386.nsx

@@ -1,31 +1,29 @@
 ETOTH-Amp_LM386
-*SPICE Netlist generated by Advanced Sim server on 03.12.2025 21:51:07
+*SPICE Netlist generated by Advanced Sim server on 08.12.2025 13:48:55
 .options MixedSimGenerated
 
 *Schematic Netlist:
-CC_DCBLOCK_IN NetC_DCBLOCK_IN_1 IN_FILT 10uF
+CC_DCBLOCK_IN IN IN_FILT 10uF
 CC_DCBLOCK_OUT NetC_DCBLOCK_OUT_1 OUT 220uF
 XIC1A NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386
 XIC1B NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386
 LL_Speaker 0 NetL_Speaker_2 0.1mH
-RR_G NetR_G_1 NetR_G_2 100k
 RR_POTA 0 NetR_POT_2 {10k * {POS}}
 RR_POTB NetR_POT_2 IN_FILT {10k - (10k * {POS})}
 RR_Speaker NetL_Speaker_2 OUT 4R
 RR_static1 NetIC1_3 NetR_POT_2 100k
 RR_static2 0 NetIC1_3 10k
-XT1 NetR_G_2 IN NetC_DCBLOCK_IN_1 BUZ-81
-VU_KBactive NetR_G_1 0 DC 0 PULSE(3.3 0 0 4u 1u 4.5m*4 4.5m*8) AC 1 0
 VU_q VAP 0 10V
 VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
 
-.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255)
-.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
-.PLOT TRAN {v(U_KBactive)} =PLOT(2) =AXIS(1) =NAME(U_KBactive) =UNITS(V)
+.PLOT AC {MAG(v(OUT))} =PLOT(1) =AXIS(1) =NAME(A_Speaker)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
-.TRAN 90.91u 180.0m 0 90.91u
+.AC DEC 50 22 22000
+.CONTROL
+SWEEP C_DCBLOCK_OUT LIST 100u 150u 220u 330u 470u 680u
+.ENDC
 
 *Global Parameters:
 .PARAM POS={1}
@@ -112,28 +110,4 @@ q14 out 10018 gnd ddnpn 100
 + Tf=1n Itf=1 Xtf=0 Vtf=10)
 .ends LM386
 
-*******
-*SRC=BUZ-81;BUZ-81;MOSFETs N;Siemens;800V 4A 2.5 Ohm
-*SYM=N-MOSFET
-.SUBCKT BUZ-81 1 2 3
-LS 5 2 7N
-LD 95 3 5N
-RG 4 11 5.5M
-RS 5 76 23M
-D81 76 95 DREV
-.MODEL DREV D CJO=0.4N RS=20M TT=625N IS=300P BV=800
-M81 86 11 76 96 MBUZ
-.MODEL MBUZ NMOS VTO=3.463 KP=3.263
-M2 11 86 8 8 MSW
-.MODEL MSW NMOS VTO=0.001 KP=5
-M3 86 11 8 8 MSW
-COX 11 8 1.3N
-DGD 8 86 DCGD
-.MODEL DCGD D CJO=0.265N M=0.495 VJ=0.975
-CGS 76 11 1N
-MRDR 86 86 95 86 MVRD
-.MODEL MVRD NMOS VTO=-24.99 KP=.022
-LG 4 1 7N
-.ENDS
-
 .END

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [ETOTH-Amp_LM386.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 20:19:33 On 03.12.2025
+Finished Output Generation At 13:33:33 On 08.12.2025

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [TRI-SQR-VCO_OTA_SS.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 17:11:02 On 03.12.2025
+Finished Output Generation At 23:56:01 On 08.12.2025

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/TRI-SQR-VCO_OTA_SS.nsx

@@ -1,5 +1,5 @@
 TRI-SQR-VCO_OTA_SS
-*SPICE Netlist generated by Advanced Sim server on 08.12.2025 14:54:01
+*SPICE Netlist generated by Advanced Sim server on 08.12.2025 23:57:13
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -63,10 +63,9 @@ RR_uC_comp_GND 0 NetR_POT_uC_comp_1 330k
 RR_uC_comp_VAP NetR_POT_uC_comp_3 VAP 330k
 RRoff_a NetIC3_2 0 1Meg
 RRoff_b NetIC3_2 0 1Meg
-QT1 NetC_an_1 VCM NetC_an_2 2N2907
-QT2 NetT2_3 U_C NetC_an_2 2N2907
+XT1 VCM NetC_an_2 NetC_an_1 U_C NetC_an_2 NetT1_6 DMMT3906W
 JT_SAW VCM fet_gate NetIC2_12 BF256B
-VU_mess NetT2_3 NetIC1_16 0
+VU_mess NetT1_6 NetIC1_16 0
 VU_MESSITOGND NetICS_2 VCM 0
 VU_messref NetR_E_2 NetIC2_7 0
 VU_single VAP 0 +10V
@@ -325,12 +324,17 @@ D3  15 24 DX
 *
 .ENDS
 
-*2N2907 MCE 5-27-97
-*Ref: Motorola Small-Signal Device databook, Q4/94
-*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
-.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
-+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
-+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
+*SRC=DMMT3906W;DI_DMMT3906W;BJTs PNP; Si;  40.0V  0.200A  257MHz   Diodes, Inc. PNP 
+.MODEL DI_DMMT3906W  PNP (IS=20.3f NF=1.00 BF=274 VAF=114 
++ IKF=36.4m ISE=6.99p NE=2.00 BR=4.00 NR=1.00 
++ VAR=20.0 IKR=90.0m RE=1.01 RB=4.03 RC=0.403 
++ XTB=1.5 CJE=12.1p VJE=1.10 MJE=0.500 CJC=10.7p VJC=0.300 
++ MJC=0.300 TF=531p TR=85.6n EG=1.12 )
+
+.SUBCKT DMMT3906W  B1 E1 C1  B2 E2 C2
+Q1 C1 B1 E1 DI_DMMT3906W
+Q2 C2 B2 E2 DI_DMMT3906W
+.ENDS DMMT3906W
 
 *PHILIPS SEMICONDUCTORS        Version: 1.0
 *Filename: bf256a_bf256b_philips

dev/da_altium_lib/DA_LIB/DMMT3906W.lib

@@ -0,0 +1,18 @@
+* Dual PNP matched pair: DMMT3906W
+* Pins: 1-B2 2-B1 3-C1 4-E1 5-E2 6-C2
+* Author: Erik Tóth <me@etoth.dev>, 2025
+
+.SUBCKT DMMT3906W  B1 E1 C1  B2 E2 C2
+
+Q1 C1 B1 E1 DI_DMMT3906W
+Q2 C2 B2 E2 DI_DMMT3906W
+
+.ENDS DMMT3906W
+
+
+*SRC=DMMT3906W;DI_DMMT3906W;BJTs PNP; Si;  40.0V  0.200A  257MHz   Diodes, Inc. PNP 
+.MODEL DI_DMMT3906W  PNP (IS=20.3f NF=1.00 BF=274 VAF=114 
++ IKF=36.4m ISE=6.99p NE=2.00 BR=4.00 NR=1.00 
++ VAR=20.0 IKR=90.0m RE=1.01 RB=4.03 RC=0.403 
++ XTB=1.5 CJE=12.1p VJE=1.10 MJE=0.500 CJC=10.7p VJC=0.300 
++ MJC=0.300 TF=531p TR=85.6n EG=1.12 )

dev/digital/.gitignore

@@ -0,0 +1 @@
+**/History

docs/README.md

@@ -19,7 +19,7 @@ In _lit_ werden alle Literaturverweise, die zur Ausarbeitung für die Diplomarbe
 Die eigentliche __Diplomarbeit__ und die dazugehörigen (finalen) Fertigungsunterlagen werden in den jeweiligen _general_ Ordnern gespeichert.
 ### Ordner Struktur
 <p>
-<a href="../">..</a><br>
+<a href="../">audio-synth</a><br>
 ├── <a href="../dev/">dev</a><br>
 │   ├── <a href="../dev/analog/">analog</a><br>
 │   ├── <a href="../dev/da_altium_lib/">da_altium_lib</a><br>
@@ -79,3 +79,4 @@ Die eigentliche __Diplomarbeit__ und die dazugehörigen (finalen) Fertigungsunte
 - V2.5 (2025-10-25, etoth): C 0603 100nF (PCB, 3D)
 - V2.6 (2025-11-25, etoth): IC LM386 (PCB, 3D, Sim)
 - V3.0 (2025-12-03, etoth): Library refactor
+- V3.1 (2025-12-08, etoth): Diverse R, C und T hinzugefügt, sonstige Bauteil normalisiert