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VCA Update mit Einbindung zu MCU

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Erik Tóth
2025-12-06 16:26:06 +01:00
parent 7c8a90ce7d
commit fcc731af4c
95 changed files with 21216 additions and 5650 deletions
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103
dev/analog/VCA_LM13700/Project Outputs for VCA_LM13700/VCA_LM13700.nsx
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@@ -1,39 +1,51 @@
VCA_LM13700
*SPICE Netlist generated by Advanced Sim server on 04.12.2025 07:35:49
*SPICE Netlist generated by Advanced Sim server on 06.12.2025 16:21:09
.options MixedSimGenerated
*Schematic Netlist:
CC1 NetC1_1 NetC1_2 220nF
CC2 Uout NetC2_2 220nF
II_abc VCM NetI_abc_2 DC 0 PULSE(150u 0 0 4u 1u 5m 10m) AC 1 0
II_db VCM NetI_db_2 1mA
XIC1A NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
+ ExtraNet_XIC1A_9 ExtraNet_XIC1A_10 Vcc ExtraNet_XIC1A_12 ExtraNet_XIC1A_13
+ ExtraNet_XIC1A_14 ExtraNet_XIC1A_15 ExtraNet_XIC1A_16 LM13700-DUAL
XIC1C NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
+ ExtraNet_XIC1C_9 ExtraNet_XIC1C_10 Vcc ExtraNet_XIC1C_12 ExtraNet_XIC1C_13
+ ExtraNet_XIC1C_14 ExtraNet_XIC1C_15 ExtraNet_XIC1C_16 LM13700-DUAL
XIC1E NetI_abc_2 NetI_db_2 NetIC1_14 NetIC1_13 NetIC1_10 0 NetIC1_10 NetC2_2
+ ExtraNet_XIC1E_9 ExtraNet_XIC1E_10 Vcc ExtraNet_XIC1E_12 ExtraNet_XIC1E_13
+ ExtraNet_XIC1E_14 ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
RR1 NetIC1_14 NetC1_2 3k
RR2 NetIC1_10 VCM 27k
RR3 NetC2_2 0 5.1k
RR4 VCM NetIC1_14 470R
RR5 VCM NetIC1_13 470R
RRc Uout 0 51k
VUin NetC1_1 VCM DC 0 SIN(0 3V 440Hz 0 0 0) AC 1 0
XIC1A NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1A_9
+ ExtraNet_XIC1A_10 VAP ExtraNet_XIC1A_12 ExtraNet_XIC1A_13 ExtraNet_XIC1A_14
+ ExtraNet_XIC1A_15 ExtraNet_XIC1A_16 LM13700-DUAL
XIC1C NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1C_9
+ ExtraNet_XIC1C_10 VAP ExtraNet_XIC1C_12 ExtraNet_XIC1C_13 ExtraNet_XIC1C_14
+ ExtraNet_XIC1C_15 ExtraNet_XIC1C_16 LM13700-DUAL
XIC1E NetIC1_16 NetIC1_15 NetIC1_14 NetIC1_13 OUT 0 OUT Uout ExtraNet_XIC1E_9
+ ExtraNet_XIC1E_10 VAP ExtraNet_XIC1E_12 ExtraNet_XIC1E_13 ExtraNet_XIC1E_14
+ ExtraNet_XIC1E_15 ExtraNet_XIC1E_16 LM13700-DUAL
RR1 NetIC1_14 IN 3k
RR2 OUT VCM 27k
RR3 Uout 0 5.1k
RR4 VCM NetIC1_14 1k
RR5 VCM NetIC1_13 1k
RR_B NetR_B_1 NetR_B_2 100k
RR_BASE_GAIN NetIC1_16 NetR_BASE_GAIN_2 10k
RR_D VAP NetIC1_15 5k
RR_GAINA NetR_BASE_GAIN_2 NetR_BASE_GAIN_2 {100k * {GAIN}}
RR_GAINB NetR_BASE_GAIN_2 NetR_GAIN_3 {100k - (100k * {GAIN})}
QT VAP NetR_B_1 NetR_GAIN_3 QBC547B
VU_VCO_EN NetR_B_2 0 DC 0 PULSE(3.3 0 0 4u 1u 20m 40m) AC 1 0
VUin IN VCM DC 0 SIN(0 2V 440Hz 0 0 0) AC 1 0
VUneg VCM 0 +5V
VUpos Vcc VCM +5V
VUpos VAP VCM +5V
.PLOT TRAN {v(Uin)} =PLOT(1) =AXIS(1) =NAME(Uin) =UNITS(V)
.PLOT TRAN {v(Rc)} =PLOT(2) =AXIS(1) =NAME(Uout) =UNITS(V)
.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(Uin) =UNITS(V)
.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(Uout) =UNITS(V)
.PLOT TRAN {v(U_VCO_EN)} =PLOT(3) =AXIS(1) =NAME(VCO_EN) =UNITS(V)
.PLOT TRAN {ie(T)} =PLOT(4) =AXIS(1) =NAME(I_ABC) =UNITS(A)
.PLOT TRAN {ib(T)} =PLOT(5) =AXIS(1) =NAME(I_B) =UNITS(A)
.PLOT TRAN {i(R5)} =PLOT(6) =AXIS(1) =NAME(I_5) =UNITS(A)
.PLOT TRAN {i(R4)} =PLOT(6) =AXIS(1) =NAME(I_4) =UNITS(A)
.OPTIONS METHOD=GEAR MAXORD=2
*Selected Circuit Analyses:
.TRAN 45u 100m 90m 45u
.TRAN 45u 100m 20m 45u
.CONTROL
SWEEP GAIN 0 1 0.1
.ENDC
*Global Parameters:
.PARAM GAIN={0.5}
*Models and Subcircuits:
* A dual opamp ngspice model
* file name: LM13700-DUAL.ckt
@@ -134,4 +146,45 @@ XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
.ends
*
.MODEL QBC547B NPN(
+ IS=2.39E-14
+ NF=1.008
+ ISE=3.545E-15
+ NE=1.541
+ BF=294.3
+ IKF=0.1357
+ VAF=63.2
+ NR=1.004
+ ISC=6.272E-14
+ NC=1.243
+ BR=7.946
+ IKR=0.1144
+ VAR=25.9
+ RB=1
+ IRB=1E-06
+ RBM=1
+ RE=0.4683
+ RC=0.85
+ XTB=0
+ EG=1.11
+ XTI=3
+ CJE=1.358E-11
+ VJE=0.65
+ MJE=0.3279
+ TF=4.391E-10
+ XTF=120
+ VTF=2.643
+ ITF=0.7495
+ PTF=0
+ CJC=3.728E-12
+ VJC=0.3997
+ MJC=0.2955
+ XCJC=0.6193
+ TR=1E-32
+ CJS=0
+ VJS=0.75
+ MJS=0.333
+ FC=0.9579 )
.END