12 Commits

Author SHA1 Message Date
f3d8940098 DA Library Update V3.1
diverse R, C, T, sonstige Normaliserungen
2025-12-09 00:05:26 +01:00
Wendelin Waldhart
0f8b964136 CV-Gate Offset for VCM as reference; Normalized Resistors according to E12 2025-12-08 14:57:13 +01:00
01da75630a Rebase fix 2025-12-06 19:56:41 +01:00
cfa96b349a Merge 2025-12-06 19:50:12 +01:00
397d84ccb7 Library Erweiterung 2025-12-06 19:45:46 +01:00
Wendelin Waldhart
798ab9fdd9 VCO Octave Shift update 2025-12-06 16:49:41 +01:00
Wendelin Waldhart
3d432392d3 VCO temp compensation, static Octave shift, uC Resolution compensation 2025-12-06 16:38:20 +01:00
fcc731af4c VCA Update mit Einbindung zu MCU
Soweit OK
2025-12-06 16:26:06 +01:00
7c8a90ce7d Impplemenation of EN-Pins for CV-Gates, Metronome 2025-12-06 11:48:11 +01:00
06fa584b6d Refactor code structure for improved readability and maintainability, imporved matrix read, improved SB button read 2025-12-06 09:03:02 +01:00
60950e6a0c Revise folder structure in README.md
Updated folder structure in README for clarity.
2025-12-04 23:00:02 +01:00
cd0699e2df Update README with folder structure and links 2025-12-04 22:59:09 +01:00
821 changed files with 27383 additions and 10627 deletions

1
dev/analog/.gitignore vendored Normal file
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**/History

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@@ -1,31 +1,29 @@
ETOTH-Amp_LM386 ETOTH-Amp_LM386
*SPICE Netlist generated by Advanced Sim server on 03.12.2025 21:51:07 *SPICE Netlist generated by Advanced Sim server on 08.12.2025 13:48:55
.options MixedSimGenerated .options MixedSimGenerated
*Schematic Netlist: *Schematic Netlist:
CC_DCBLOCK_IN NetC_DCBLOCK_IN_1 IN_FILT 10uF CC_DCBLOCK_IN IN IN_FILT 10uF
CC_DCBLOCK_OUT NetC_DCBLOCK_OUT_1 OUT 220uF CC_DCBLOCK_OUT NetC_DCBLOCK_OUT_1 OUT 220uF
XIC1A NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386 XIC1A NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386
XIC1B NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386 XIC1B NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386
LL_Speaker 0 NetL_Speaker_2 0.1mH LL_Speaker 0 NetL_Speaker_2 0.1mH
RR_G NetR_G_1 NetR_G_2 100k
RR_POTA 0 NetR_POT_2 {10k * {POS}} RR_POTA 0 NetR_POT_2 {10k * {POS}}
RR_POTB NetR_POT_2 IN_FILT {10k - (10k * {POS})} RR_POTB NetR_POT_2 IN_FILT {10k - (10k * {POS})}
RR_Speaker NetL_Speaker_2 OUT 4R RR_Speaker NetL_Speaker_2 OUT 4R
RR_static1 NetIC1_3 NetR_POT_2 100k RR_static1 NetIC1_3 NetR_POT_2 100k
RR_static2 0 NetIC1_3 10k RR_static2 0 NetIC1_3 10k
XT1 NetR_G_2 IN NetC_DCBLOCK_IN_1 BUZ-81
VU_KBactive NetR_G_1 0 DC 0 PULSE(3.3 0 0 4u 1u 4.5m*4 4.5m*8) AC 1 0
VU_q VAP 0 10V VU_q VAP 0 10V
VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0 VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255) .PLOT AC {MAG(v(OUT))} =PLOT(1) =AXIS(1) =NAME(A_Speaker)
.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
.PLOT TRAN {v(U_KBactive)} =PLOT(2) =AXIS(1) =NAME(U_KBactive) =UNITS(V)
.OPTIONS METHOD=GEAR MAXORD=2 .OPTIONS METHOD=GEAR MAXORD=2
*Selected Circuit Analyses: *Selected Circuit Analyses:
.TRAN 90.91u 180.0m 0 90.91u .AC DEC 50 22 22000
.CONTROL
SWEEP C_DCBLOCK_OUT LIST 100u 150u 220u 330u 470u 680u
.ENDC
*Global Parameters: *Global Parameters:
.PARAM POS={1} .PARAM POS={1}
@@ -112,28 +110,4 @@ q14 out 10018 gnd ddnpn 100
+ Tf=1n Itf=1 Xtf=0 Vtf=10) + Tf=1n Itf=1 Xtf=0 Vtf=10)
.ends LM386 .ends LM386
*******
*SRC=BUZ-81;BUZ-81;MOSFETs N;Siemens;800V 4A 2.5 Ohm
*SYM=N-MOSFET
.SUBCKT BUZ-81 1 2 3
LS 5 2 7N
LD 95 3 5N
RG 4 11 5.5M
RS 5 76 23M
D81 76 95 DREV
.MODEL DREV D CJO=0.4N RS=20M TT=625N IS=300P BV=800
M81 86 11 76 96 MBUZ
.MODEL MBUZ NMOS VTO=3.463 KP=3.263
M2 11 86 8 8 MSW
.MODEL MSW NMOS VTO=0.001 KP=5
M3 86 11 8 8 MSW
COX 11 8 1.3N
DGD 8 86 DCGD
.MODEL DCGD D CJO=0.265N M=0.495 VJ=0.975
CGS 76 11 1N
MRDR 86 86 95 86 MVRD
.MODEL MVRD NMOS VTO=-24.99 KP=.022
LG 4 1 7N
.ENDS
.END .END

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@@ -7,4 +7,4 @@ From : Project [ETOTH-Amp_LM386.PrjPcb]
Files Generated : 1 Files Generated : 1
Documents Printed : 0 Documents Printed : 0
Finished Output Generation At 20:19:33 On 03.12.2025 Finished Output Generation At 13:33:33 On 08.12.2025

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