Merge branch 'main' of https://github.com/erik-toth/audio-synth

Refactor 3D PCB, removing unused components

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/ETOTH-Amp_LM386.nsx

@@ -1,98 +1,32 @@
 ETOTH-Amp_LM386
-*SPICE Netlist generated by Advanced Sim server on 21.11.2025 08:22:05
+*SPICE Netlist generated by Advanced Sim server on 28.11.2025 11:11:11
 .options MixedSimGenerated
 
 *Schematic Netlist:
-CC1 NetC1_1 NetC1_2 47nF
+CC_DCBLOCK_IN IN NetC_DCBLOCK_IN_2 10uF
-CC_VCM1 NetC_VCM1_1 GND 47uF
+CC_DCBLOCK_OUT NetC_DCBLOCK_OUT_1 OUT 220uF
-CC_VCM2 VAP NetC_VCM1_1 47uF
+XIC1A NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386
-CCblock NetC1_2 NetCblock_2 220uF
+XIC1B NetIC1_1 0 NetIC1_3 0 NetC_DCBLOCK_OUT_1 VAP NetIC1_7 NetIC1_8 lm386
-CCblock1 NetCblock1_1 NetCblock1_2 47uF
+LL_Speaker 0 NetL_Speaker_2 0.1mH
-XIC1C NetIC1_10 NetC_VCM1_1 VAP GND NetIC1_8 TL074
-XIC2 NetIC2_1 GND NetCblock1_2 GND NetC1_2 VAP NetIC2_7 NetIC2_8 LM386
-LL_Speaker GND NetL_Speaker_2 0.1mH
-RR1 NetC1_1 GND 10R
 RR_POTA 0 NetR_POT_2 {10k * {POS}}
-RR_POTB NetR_POT_2 NetR_POT_3 {10k - (10k * {POS})}
+RR_POTB NetR_POT_2 NetC_DCBLOCK_IN_2 {10k - (10k * {POS})}
-RR_rs1 NetIC1_10 VAP 470k
+RR_Speaker NetL_Speaker_2 OUT 8R
-RR_rs2 GND NetIC1_10 470k
+RR_static1 NetIC1_3 NetR_POT_2 100k
-RR_Speaker NetL_Speaker_2 NetCblock_2 8R
+RR_static2 0 NetIC1_3 10k
-RR_static1 NetCblock1_1 NetR_POT_2 9400R
+VU_q VAP 0 10V
-RR_static2 0 NetCblock1_1 600R
+VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
-QT_rsN GND NetIC1_8 NetC_VCM1_1 2N2907
-QT_rsP VAP NetIC1_8 NetC_VCM1_1 2N2222
-VU_q VAP GND 10V
-VU_VCM_CURRENT 0 NetC_VCM1_1 0
-VUin NetR_POT_3 0 DC 0 SIN(0 2 440Hz 0 0 0) AC 1 0
 
-.PLOT TRAN {v(R_Speaker)+v(L_Speaker)} =PLOT(1) =AXIS(1) =NAME(U_speaker) =UNITS(V) =RGB(0, 255, 0)
+.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255)
-.PLOT TRAN {i(R_Speaker)} =PLOT(2) =AXIS(1) =NAME(I_speaker) =UNITS(A)
+.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
-.PLOT TRAN {p(R_Speaker)} =PLOT(3) =AXIS(1) =NAME(P_speaker) =UNITS(W)
-.PLOT TRAN {i(U_VCM_CURRENT)} =PLOT(4) =AXIS(1) =NAME(I_VCM) =UNITS(A)
-.PLOT TRAN {v(VAP)} =PLOT(1) =AXIS(1) =RGB(255, 0, 0)
-.PLOT TRAN {v(GND)} =PLOT(1) =AXIS(1) =RGB(0, 0, 255)
-.PLOT TRAN {i(Cblock1)} =PLOT(5) =AXIS(1) =NAME(I_C_in) =UNITS(A)
-.PLOT TRAN {v(Cblock1)} =PLOT(5) =AXIS(2) =NAME(U_C_in) =UNITS(V)
-.PLOT TRAN {i(Cblock1)} =PLOT(5) =AXIS(1) =NAME(I_C_out) =UNITS(A)
-.PLOT TRAN {v(Cblock1)} =PLOT(5) =AXIS(2) =NAME(U_C_out) =UNITS(V)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
-.TRAN 45.45u 22.73m 0 45.45u
+.TRAN 90.91u 22.73m 0 90.91u
 
 *Global Parameters:
 .PARAM POS={1}
 
 *Models and Subcircuits:
-*TL074
-*Quad LoNoise JFETInput OpAmp pkg:DIP14
-*+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
-* Connections:
-*             Non-Inverting Input
-*             | Inverting Input
-*             | | Positive Power Supply
-*             | | | Negative Power Supply
-*             | | | | Output
-*             | | | | |
-.SUBCKT TL074 1 2 3 4 5
-C1   11 12 3.498E-12
-C2    6  7 15E-12
-DC    5 53 DX
-DE   54  5 DX
-DLP  90 91 DX
-DLN  92 90 DX
-DP    4  3 DX
-BGND 99  0 V=V(3)*.5 + V(4)*.5
-BB    7 99 I=I(VB)*4.715E6 - I(VC)*5E6 + I(VE)*5E6 +
-+              I(VLP)*5E6 - I(VLN)*5E6
-GA    6  0 11 12 282.8E-6
-GCM   0  6 10 99 8.942E-9
-ISS   3 10 DC 195E-6
-HLIM 90  0 VLIM 1K
-J1   11  2 10 JX
-J2   12  1 10 JX
-R2    6  9 100E3
-RD1   4 11 3.536E3
-RD2   4 12 3.536E3
-RO1   8  5 150
-RO2   7 99 150
-RP    3  4 2.143E3
-RSS  10 99 1.026E6
-VB    9  0 DC 0
-VC    3 53 DC 2.2
-VE   54  4 DC 2.2
-VLIM  7  8 DC 0
-VLP  91  0 DC 25
-VLN   0 92 DC 25
-.MODEL DX D(IS=800E-18)
-.MODEL JX PJF(IS=15E-12 BETA=270.1E-6 VTO=-1)
-.ENDS TL074
-
-*TopSPICE library: Models\MISCSEMI.MDB
-*PART NUMBER: LM386
-*MODEL NAME:  LM386
-*SYMBOL:      X8PIN
-*
 *LM386 Audio power amplifier
 * /*
 * 1.  The following model behavior shows good agreement with the
@@ -103,9 +37,9 @@ VLN   0 92 DC 25
 *   c) Power-supply rejection ratio, both bypassed and unbypassed;
 *   d) Voltage gain, both with pins 1&8 shorted and open; and
 *   e) Total harmonic distortion.
-* 
+*
 * 2.  The model has the following discrepancies:
-* 
+*
 *   f) High-gain frequency response looks somewhat more wideband
 *      than the actual device;
 *   g) Peak-to-peak output voltage swing is a bit more than the
@@ -114,13 +48,13 @@ VLN   0 92 DC 25
 *   h) Input bias current in this model is only about 7 nA,
 *      compared with the 250 nA "typical" value mentioned in
 *      the data sheet.
-* 
+*
 * 3.  The frequency response characteristics of this LM386 model
 * can be adjusted somewhat by changing C1, the rolloff capacitor in
 * the voltage gain stage.  It could also be made more realistic by
 * tweaking transistor model parameters Cjc, Cje, Tr and Tf,
 * although this can get pretty hairy.
-* 
+*
 * 4.  Likewise, output drive capability could be made more
 * realistic by tweaking transistor model parameters; again, this is
 * hairy.
@@ -174,18 +108,4 @@ q14 out 10018 gnd ddnpn 100
 + Tf=1n Itf=1 Xtf=0 Vtf=10)
 .ends LM386
 
-*2N2907 MCE 5-27-97
-*Ref: Motorola Small-Signal Device databook, Q4/94
-*Si 400mW 40V 600mA 250MHz GenPurp pkg:TO-18 3,2,1
-.MODEL 2N2907 PNP (IS=60.9F NF=1 BF=260 VAF=114 IKF=0.36 ISE=30.2P NE=2
-+ BR=4 NR=1 VAR=20 IKR=0.54 RE=85.8M RB=0.343 RC=34.3M XTB=1.5
-+ CJE=27.6P VJE=1.1 MJE=0.5 CJC=15.3P VJC=0.3 MJC=0.3 TF=636P TR=442N)
-
-*2N2222 MCE 5-20-97
-*Ref: Motorola Small-Signal Device Databook, Q4/94
-*Si 400mW 30V 800mA 300MHz GenPurp pkg:TO-18 3,2,1
-.MODEL 2N2222 NPN (IS=81.2F NF=1 BF=195 VAF=98.6 IKF=0.48 ISE=53.7P NE=2
-+ BR=4 NR=1 VAR=20 IKR=0.72 RE=64.4M RB=0.258 RC=25.8M XTB=1.5
-+ CJE=89.5P VJE=1.1 MJE=0.5 CJC=28.9P VJC=0.3 MJC=0.3 TF=530P TR=368N)
-
 .END

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [ETOTH-Amp_LM386.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 08:00:57 On 21.11.2025
+Finished Output Generation At 11:00:20 On 28.11.2025

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [TRI-SQR-VCO_OTA_SS.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 21:27:47 On 23.10.2025
+Finished Output Generation At 12:23:27 On 28.11.2025

dev/analog/ETOTH-TRI-SQR-VCO_OTA_SS/Project Outputs for TRI-SQR-VCO_OTA_SS/TRI-SQR-VCO_OTA_SS.nsx

@@ -1,170 +1,79 @@
 TRI-SQR-VCO_OTA_SS
-*SPICE Netlist generated by Advanced Sim server on 18.11.2025 14:07:43
+*SPICE Netlist generated by Advanced Sim server on 02.12.2025 15:10:05
 .options MixedSimGenerated
 
 *Schematic Netlist:
-CC NetC_1 0 4.7nF
+CC NetC_1 VCM 4.7nF
 CC_an NetC_an_1 NetC_an_2 1nF
-XIC1A NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 GND NetC_1 U_TRI ExtraNet_XIC1A_9
+XIC1A NetIC1_16 NetIC1_15 U_SQR_OTA VCM NetC_1 0 NetC_1 U_TRI ExtraNet_XIC1A_9
 + ExtraNet_XIC1A_10 VAP U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
-XIC1B NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 GND NetC_1 U_TRI ExtraNet_XIC1B_9
+XIC1B NetIC1_16 NetIC1_15 U_SQR_OTA VCM NetC_1 0 NetC_1 U_TRI ExtraNet_XIC1B_9
 + ExtraNet_XIC1B_10 VAP U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
-XIC1C NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 GND NetC_1 U_TRI ExtraNet_XIC1C_9
+XIC1C NetIC1_16 NetIC1_15 U_SQR_OTA VCM NetC_1 0 NetC_1 U_TRI ExtraNet_XIC1C_9
 + ExtraNet_XIC1C_10 VAP U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
-XIC1E NetIC1_16 NetIC1_15 U_SQR_OTA 0 NetC_1 GND NetC_1 U_TRI ExtraNet_XIC1E_9
+XIC1E NetIC1_16 NetIC1_15 U_SQR_OTA VCM NetC_1 0 NetC_1 U_TRI ExtraNet_XIC1E_9
 + ExtraNet_XIC1E_10 VAP U_SQR_OTA U_TRI U_SQR_OTA NetIC1_2 NetIC1_1 LM13700-DUAL
-XIC2A U_SQR_OTA U_SQR VAP GND U_SQR TL074
+XIC2A U_SQR_OTA U_SQR VAP 0 U_SQR TL074
-XIC2B 0 NetC_an_1 VAP GND NetIC2_7 TL074
+XIC2B VCM NetC_an_1 VAP 0 NetIC2_7 TL074
-XIC2C 0 NetIC2_9 VAP GND U_C TL074
+XIC2C NetIC2_10 NetIC2_9 VAP 0 U_CV TL074
-XIC2D NetIC2_12 NetIC2_13 VAP GND U_SAW TL074
+XIC2D NetIC2_12 NetIC2_13 VAP 0 U_SAW TL074
-XIC3A 0 NetIC3_2 VAP GND U_in TL074
+XIC3A VCM NetIC3_2 VAP 0 U_in TL074
-XIC3B U_SAW NetIC3_6 VAP GND NetIC3_7 TL074
+XIC3B U_SAW NetIC3_6 VAP 0 NetIC3_7 TL074
-XICSA R.VMID NetICS_2 VAP GND NetICS_2 LF411
+XIC3C VCM NetIC3_9 VAP 0 U_C TL074
-XICSB R.VMID NetICS_2 VAP GND NetICS_2 LF411
+XICSA R.VMID NetICS_2 VAP 0 NetICS_2 LF411
-RR2 GND U_TRI 22k
+XICSB R.VMID NetICS_2 VAP 0 NetICS_2 LF411
+RR2 0 U_TRI 22k
 RR3 VAP NetIC1_1 15k
 RR4a NetIC3_2 U_TRI 100k
 RR4b U_in NetIC3_2 50k
-RR_A 0 U_SQR_OTA 3.63k
+RR_A VCM U_SQR_OTA 3.63k
-RR_CV NetR_CV_1 NetIC2_9 59.941k
+RR_CV U_CV NetIC3_9 55k
 RR_E NetC_an_2 NetR_E_2 10k
-RR_lambda_T NetIC2_9 U_C 1.1k
+RR_lambda_T NetIC3_9 U_C 1k
-RR_PWM_a GND NetIC3_6 15k
+RR_off_a VCM NetIC2_10 1k
+RR_off_b NetIC2_9 U_CV 1k
+RR_off_c 0 NetIC2_9 1k
+RR_off_d NetR_off_d_1 NetIC2_10 1k
+RR_PWM_a 0 NetIC3_6 15k
 RR_PWM_b NetIC3_6 VAP 10k
 RR_PWM_c U_PWM NetIC3_7 1k
-RR_PWM_d 0 U_PWM 2k
+RR_PWM_d VCM U_PWM 2k
-RR_ref NetC_an_1 GND 524.8k
+RR_ref NetC_an_1 0 524.8k
 RR_S1 R.VMID VAP 220k
-RR_S2 GND R.VMID 220k
+RR_S2 0 R.VMID 220k
 RR_SAW_a NetIC2_13 U_in 10k
 RR_SAW_b NetIC2_12 U_in 10k
 RR_SAW_c U_SAW NetIC2_13 10k
 RR_SAW_e U_SQR fet_gate 33k
-RR_SAW_f GND fet_gate 100k
+RR_SAW_f 0 fet_gate 100k
-RRoff NetIC3_2 GND 250k
+RRoff NetIC3_2 0 250k
-QT1 NetC_an_1 0 NetC_an_2 2N2907
+QT1 NetC_an_1 VCM NetC_an_2 2N2907
 QT2 NetT2_3 U_C NetC_an_2 2N2907
-JT_SAW 0 fet_gate NetIC2_12 BF256B
+JT_SAW VCM fet_gate NetIC2_12 BF256B
 VU_mess NetT2_3 NetIC1_16 0
-VU_MESSITOGND NetICS_2 0 0
+VU_MESSITOGND NetICS_2 VCM 0
 VU_messref NetR_E_2 NetIC2_7 0
-VU_single VAP GND +10V
+VU_single VAP 0 +10V
-VU_var NetR_CV_1 0 1
+VU_var NetR_off_d_1 0 1
 
 .PLOT TRAN {v(U_SQR)} =PLOT(1) =AXIS(1) =NAME(U_SQR) =UNITS(V)
 .PLOT TRAN {v(U_TRI)} =PLOT(2) =AXIS(1) =NAME(U_TRI) =UNITS(V)
 .PLOT TRAN {v(U_SAW)} =PLOT(3) =AXIS(1) =NAME(U_SAW) =UNITS(V)
 .PLOT TRAN {v(U_PWM)} =PLOT(4) =AXIS(1) =NAME(U_PWM) =UNITS(V)
-.PLOT TRAN {i(U_mess)} =PLOT(5) =AXIS(1) =NAME(I_GND) =UNITS(A)
+.PLOT TRAN {v(U_C)} =PLOT(5) =AXIS(1) =NAME(Uc) =UNITS(V)
-.PLOT TRAN {v(U_in)} =PLOT(2) =AXIS(1) =NAME(U_in) =UNITS(V)
+.PLOT TRAN {i(U_mess)} =PLOT(6) =AXIS(1) =NAME(i_abc) =UNITS(A)
 
 .OPTIONS ABSTOL=1e-10 RELTOL=1e-2 VNTOL=1e-4 METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
-.TRAN 25u 20m 5m 25u UIC
+.TRAN 10u 20m 5m 10u
+.CONTROL
+SWEEP U_var LIST 1
+.ENDC
 
 *Global Parameters:
 .PARAM POS=0
 
 *Models and Subcircuits:
-* A dual opamp ngspice model
-* file name: LM13700-DUAL.ckt
-.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
-+ 2out 2in- 2in+ 2Dbias 2ABin
-*//////////////////////////////////////////////////////////////////////
-* (C) National Semiconductor, Inc.
-* Models developed and under copyright by:
-* National Semiconductor, Inc.
-*/////////////////////////////////////////////////////////////////////
-* Legal Notice: This material is intended for free software support.
-* The file may be copied, and distributed; however, reselling the 
-*  material is illegal
-
-*////////////////////////////////////////////////////////////////////
-* For ordering or technical information on these models, contact:
-* National Semiconductor's Customer Response Center
-*                 7:00 A.M.--7:00 P.M.  U.S. Central Time
-*                                (800) 272-9959
-* For Applications support, contact the Internet address:
-*  amps-apps@galaxy.nsc.com
-
-* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\            
-* LM13700 Dual Operational Transconductance Amplifier                 
-* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\                 
-*
-*                   Amplifier Bias Input
-*                   | Diode Bias
-*                   | | Positive Input
-*                   | | | Negative Input
-*                   | | | | Output
-*                   | | | | | Negative power supply
-*                   | | | | | | Buffer Input
-*                   | | | | | | | Buffer Output
-*                   | | | | | | | | Positive power supply
-*                   | | | | | | | | |
-.SUBCKT LM13700/NS  1 2 3 4 5 6 7 8 11
-*
-* Features:
-* gm adjustable over 6 decades.
-* Excellent gm linearity.
-* Linearizing diodes.
-* Wide supply range of +/-2V to +/-22V.
-*
-* Note:  This model is single-pole in nature and over-estimates
-*       AC bandwidth and phase margin (stability) by over 2X.   
-*       Although refinement may be possible in the future, please
-*       use benchtesting to finalize AC circuit design.
-* 
-* Note: Model is for single device only and simulated
-*       supply current is 1/2 of total device current.
-*
-******************************************************
-* 
-C1  6  4  4.8P
-C2  3  6  4.8P
-* Output capacitor  
-C3  5  6  6.26P                                       
-D1  2  4  DX
-D2  2  3  DX
-D3  11 21 DX
-D4  21 22 DX
-D5  1  26 DX
-D6  26 27 DX
-D7  5  29 DX
-D8  28 5  DX
-D10 31 25 DX
-* Clamp for -CMR  
-D11 28 25 DX                                        
-* Ios source 
-F1  4  3  POLY(1)   V6 1E-10 5.129E-2 -1.189E4 1.123E9 
-F2  11 5  V2        1.022
-F3  25 6  V3        1.0
-F4  5  6  V1        1.022
-* Output impedance 
-F5  5  0  POLY(2)   V3 V7 0 0 0 0 1                  
-G1  0  33 5         0 .55E-3
-I1  11 6  300U
-Q1  24 32 31        QX1
-Q2  23 3  31        QX2
-Q3  11 7  30        QZ
-Q4  11 30 8         QY
-V1  22 24 0V
-V2  22 23 0V
-V3  27 6  0V
-V4  11 29 1.4
-V5  28 6  1.2
-V6  4  32 0V
-V7  33 0  0V
-.MODEL QX1 NPN (IS=5E-16     BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
-.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
-.MODEL QY  NPN (IS=6E-15     BF=50)
-.MODEL QZ  NPN (IS=5E-16     BF=266)  
-.MODEL DX  D   (IS=5E-16)
-.ENDS
-*$
-XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
-XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
-.ends
-
 *TL074
 *Quad LoNoise JFETInput OpAmp pkg:DIP14
 *+ (A:3,2,4,11,1)(B:5,6,4,11,7)(C:10,9,4,11,8)(D:12,13,4,11,14)
@@ -332,4 +241,104 @@ D3  15 24 DX
 +              FC = 5.00000E-001
 +)
 
+*Cached Models and Subcircuits:
+* A dual opamp ngspice model
+* file name: LM13700-DUAL.ckt
+.subckt LM13700-DUAL 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout 2Bout 2Bin vcc+
++ 2out 2in- 2in+ 2Dbias 2ABin
+*//////////////////////////////////////////////////////////////////////
+* (C) National Semiconductor, Inc.
+* Models developed and under copyright by:
+* National Semiconductor, Inc.
+*/////////////////////////////////////////////////////////////////////
+* Legal Notice: This material is intended for free software support.
+* The file may be copied, and distributed; however, reselling the 
+*  material is illegal
+
+*////////////////////////////////////////////////////////////////////
+* For ordering or technical information on these models, contact:
+* National Semiconductor's Customer Response Center
+*                 7:00 A.M.--7:00 P.M.  U.S. Central Time
+*                                (800) 272-9959
+* For Applications support, contact the Internet address:
+*  amps-apps@galaxy.nsc.com
+
+* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\            
+* LM13700 Dual Operational Transconductance Amplifier                 
+* \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\                 
+*
+*                   Amplifier Bias Input
+*                   | Diode Bias
+*                   | | Positive Input
+*                   | | | Negative Input
+*                   | | | | Output
+*                   | | | | | Negative power supply
+*                   | | | | | | Buffer Input
+*                   | | | | | | | Buffer Output
+*                   | | | | | | | | Positive power supply
+*                   | | | | | | | | |
+.SUBCKT LM13700/NS  1 2 3 4 5 6 7 8 11
+*
+* Features:
+* gm adjustable over 6 decades.
+* Excellent gm linearity.
+* Linearizing diodes.
+* Wide supply range of +/-2V to +/-22V.
+*
+* Note:  This model is single-pole in nature and over-estimates
+*       AC bandwidth and phase margin (stability) by over 2X.   
+*       Although refinement may be possible in the future, please
+*       use benchtesting to finalize AC circuit design.
+* 
+* Note: Model is for single device only and simulated
+*       supply current is 1/2 of total device current.
+*
+******************************************************
+* 
+C1  6  4  4.8P
+C2  3  6  4.8P
+* Output capacitor  
+C3  5  6  6.26P                                       
+D1  2  4  DX
+D2  2  3  DX
+D3  11 21 DX
+D4  21 22 DX
+D5  1  26 DX
+D6  26 27 DX
+D7  5  29 DX
+D8  28 5  DX
+D10 31 25 DX
+* Clamp for -CMR  
+D11 28 25 DX                                        
+* Ios source 
+F1  4  3  POLY(1)   V6 1E-10 5.129E-2 -1.189E4 1.123E9 
+F2  11 5  V2        1.022
+F3  25 6  V3        1.0
+F4  5  6  V1        1.022
+* Output impedance 
+F5  5  0  POLY(2)   V3 V7 0 0 0 0 1                  
+G1  0  33 5         0 .55E-3
+I1  11 6  300U
+Q1  24 32 31        QX1
+Q2  23 3  31        QX2
+Q3  11 7  30        QZ
+Q4  11 30 8         QY
+V1  22 24 0V
+V2  22 23 0V
+V3  27 6  0V
+V4  11 29 1.4
+V5  28 6  1.2
+V6  4  32 0V
+V7  33 0  0V
+.MODEL QX1 NPN (IS=5E-16     BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
+.MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2)
+.MODEL QY  NPN (IS=6E-15     BF=50)
+.MODEL QZ  NPN (IS=5E-16     BF=266)  
+.MODEL DX  D   (IS=5E-16)
+.ENDS
+*$
+XU1C 1ABin 1DBias 1in+ 1in- 1out vcc- 1Bin 1Bout vcc+ LM13700/NS
+XU1A 2ABin 2DBias 2in+ 2in- 2out vcc- 2Bin 2Bout vcc+ LM13700/NS
+.ends
+
 .END