Update TO-DO list and version history in README

TOP done; MCU done; CV_GEN done; VCO done; PM done; VCA done; OS done; waiting for VCF; EXT waiting until VCF done

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/ETOTH-Amp_LM386.nsx

@@ -1,5 +1,5 @@
 ETOTH-Amp_LM386
-*SPICE Netlist generated by Advanced Sim server on 08.12.2025 13:48:55
+*SPICE Netlist generated by Advanced Sim server on 17.12.2025 16:45:18
 .options MixedSimGenerated
 
 *Schematic Netlist:
@@ -11,18 +11,19 @@ LL_Speaker 0 NetL_Speaker_2 0.1mH
 RR_POTA 0 NetR_POT_2 {10k * {POS}}
 RR_POTB NetR_POT_2 IN_FILT {10k - (10k * {POS})}
 RR_Speaker NetL_Speaker_2 OUT 4R
-RR_static1 NetIC1_3 NetR_POT_2 100k
+RR_static1 NetIC1_3 NetR_POT_2 75k
 RR_static2 0 NetIC1_3 10k
 VU_q VAP 0 10V
 VUin IN 0 DC 0 SIN(5 2 220 0 0 0) AC 1 0
 
-.PLOT AC {MAG(v(OUT))} =PLOT(1) =AXIS(1) =NAME(A_Speaker)
+.PLOT TRAN {v(IN)} =PLOT(1) =AXIS(1) =NAME(U_IN) =UNITS(V) =RGB(0, 0, 255)
+.PLOT TRAN {v(OUT)} =PLOT(2) =AXIS(1) =NAME(U_OUT) =UNITS(V) =RGB(255, 153, 0)
 
 .OPTIONS METHOD=GEAR MAXORD=2
 *Selected Circuit Analyses:
-.AC DEC 50 22 22000
+.TRAN 90.91u 22.73m 0 90.91u
 .CONTROL
-SWEEP C_DCBLOCK_OUT LIST 100u 150u 220u 330u 470u 680u
+SWEEP POS LIST 1
 .ENDC
 
 *Global Parameters:

dev/analog/ETOTH-Amp_LM386/Project Outputs for ETOTH-Amp_LM386/Status Report.Txt

@@ -7,4 +7,4 @@ From  : Project [ETOTH-Amp_LM386.PrjPcb]
 Files Generated   : 1
 Documents Printed : 0
 
-Finished Output Generation At 13:33:33 On 08.12.2025
+Finished Output Generation At 16:43:39 On 17.12.2025

dev/general/MainSys/EXT.Harness

@@ -1,2 +0,0 @@
-VCO_CTRL_1=OFFSET_SEL_PA,OFFSET_SEL_P1,OFFSET_SEL_P4,OFFSET_SEL_P7,OFFSET_SEL_P10,POT_FINE_A,POT_FINE_B,POT_IREF,POT_PWM_ADJ,IN_TRI,IN_SAW,IN_SQR,IN_PWM,OUT
-VCO_CTRL_2=OFFSET_SEL_PA,OFFSET_SEL_P1,OFFSET_SEL_P4,OFFSET_SEL_P7,OFFSET_SEL_P10,POT_FINE_A,POT_FINE_B,POT_IREF,POT_PWM_ADJ,IN_TRI,IN_SAW,IN_SQR,IN_PWM,OUT

dev/general/MainSys/MCU.Harness

@@ -1,2 +1,2 @@
-BPM=BPM.VALUE,BPM.LED,BPM.BUTTON
+BPM=VALUE,LED,BUTTON
 SB=R1,P1,R2,P2,REC

dev/general/MainSys/MainSys.PrjPcb

@@ -271,7 +271,7 @@ GenerateClassCluster=0
 DocumentUniqueId=
 
 [Document14]
-DocumentPath=EXT.Harness
+DocumentPath=OS.Harness
 AnnotationEnabled=1
 AnnotateStartValue=1
 AnnotationIndexControlEnabled=0
@@ -288,7 +288,7 @@ GenerateClassCluster=0
 DocumentUniqueId=
 
 [Document15]
-DocumentPath=OS.Harness
+DocumentPath=VCA.Harness
 AnnotationEnabled=1
 AnnotateStartValue=1
 AnnotationIndexControlEnabled=0

dev/general/MainSys/MainSys.PrjPcbStructure

@@ -5,7 +5,7 @@ Record=SheetSymbol|SourceDocument=TOP.SchDoc|Designator=OS|SchDesignator=OS|File
 Record=SheetSymbol|SourceDocument=TOP.SchDoc|Designator=PM|SchDesignator=PM|FileName=PM.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=PM.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=TOP.SchDoc|Designator=SC1|SchDesignator=SC1|FileName=SC.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=SC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=TOP.SchDoc|Designator=SC2|SchDesignator=SC2|FileName=SC.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=SC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=TOP.SchDoc|Designator=VCA|SchDesignator=VCA|FileName=VCA.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=VCA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=MCU.SchDoc|Designator=CV_GEN|SchDesignator=CV_GEN|FileName=CV_GEN.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=CV_GEN.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
-Record=SheetSymbol|SourceDocument=SC.SchDoc|Designator=VCA|SchDesignator=VCA|FileName=VCA.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=VCA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=SC.SchDoc|Designator=VCF|SchDesignator=VCF|FileName=VCF.SchDoc|SheetNumber=7|SymbolType=Normal|RawFileName=VCF.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
 Record=SheetSymbol|SourceDocument=SC.SchDoc|Designator=VCO|SchDesignator=VCO|FileName=VCO.SchDoc|SheetNumber=6|SymbolType=Normal|RawFileName=VCO.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 

dev/general/MainSys/Project Logs for MainSys/MCU SCH ECO 18.12.2025 16-13-16.LOG

@@ -0,0 +1 @@
+Replace Part J? J HEADER_3x1 in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\MCU.SchDoc with J HEADER_3x1 from DA_LIB.IntLib

dev/general/MainSys/VCA.Harness

@@ -0,0 +1,2 @@
+GAIN1=POT_GAIN_A,POT_GAIN_B
+GAIN2=POT_GAIN_A,POT_GAIN_B

dev/general/MainSys/VCO.Harness

@@ -1 +1 @@
-VCO_CTRL=OFFSET_SEL_PA,OFFSET_SEL_P1,OFFSET_SEL_P4,OFFSET_SEL_P7,OFFSET_SEL_P10,POT_FINE_A,POT_FINE_B,POT_IREF,POT_PWM_ADJ,IN_TRI,IN_SAW,IN_SQR,IN_PWM,OUT
+VCO_CTRL=OFFSET_SEL_PA,OFFSET_SEL_P1,OFFSET_SEL_P4,OFFSET_SEL_P7,OFFSET_SEL_P10,POT_FINE_A,POT_FINE_B,POT_PWM_ADJ,IN_TRI,IN_SAW,IN_SQR,IN_PWM,OUT

docs/README.md

@@ -60,7 +60,7 @@ Die eigentliche __Diplomarbeit__ und die dazugehörigen (finalen) Fertigungsunte
 - [x] Literaturrechreche
 - [x] Schaltungsentwurf
 - [x] Simulationen
-- [ ] Gesamt System zusammengeführt
+- [x] Gesamt System zusammengeführt
 - [ ] Prototyp entwickeln und bestellen (Deadline: Bis Weihnachtsferien)
 - [ ] Start Diplomarbeit dokumentieren
 - [ ] Ende Diplomarbeit
@@ -82,3 +82,4 @@ Die eigentliche __Diplomarbeit__ und die dazugehörigen (finalen) Fertigungsunte
 - V3.0 (2025-12-03, etoth): Library refactor
 - V3.1 (2025-12-08, etoth): Diverse R, C und T hinzugefügt, sonstige Bauteil normalisiert
 - V3.2 (2025-12-14, etoth): Weitere benötigte R, C hinzugefügt; Matched-Pair hinzugefügt
+- V3.3 (2025-12-18, etoth): Diverse R und R_POT / R_TRIM; C divers; Header