Files
audio-synth/dev/general/MainSys/Project Logs for MainSys/TOP SCH ECO 12.12.2025 21-09-41.LOG
Erik Tóth 8999384170 Further additions general schematics
MCU mostly done; VCO mostly done; PM mostly done; started OS; going to begin VCA; waiting for VCF
2025-12-13 11:36:54 +01:00

398 B