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audio-synth/dev/general/MainSys/Project Logs for MainSys/PCB1 PCB ECO 12.12.2025 22-34-32.LOG
Erik Tóth 8999384170 Further additions general schematics 
MCU mostly done; VCO mostly done; PM mostly done; started OS; going to begin VCA; waiting for VCF
2025-12-13 11:36:54 +01:00

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