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audio-synth/dev/general/MainSys/Project Logs for MainSys/EXT SCH ECO 26.12.2025 22-49-56.LOG
Erik Tóth c661422a10 PCB WIP 2
All routing done, ready for review regarding the schematics, still have to do some silk screens...
2025-12-27 01:02:47 +01:00

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536 B
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Replace Part J4 J 2.54-2*12P in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\EXT.SchDoc with J 2.54-2*12P from DA_LIB.IntLib
Replace Part J5 J 2.54-2*12P in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\EXT.SchDoc with J 2.54-2*12P from DA_LIB.IntLib
Replace Part J6 J 2.54-2*6P in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\EXT.SchDoc with J 2.54-2*6P from DA_LIB.IntLib
Replace Part J7 J 2.54-2*6P in C:\HTL\5AHEL\DA\github\audio-synth\dev\general\MainSys\EXT.SchDoc with J 2.54-2*6P from DA_LIB.IntLib